[myhdl-list] Next Python to VHDL generator by using LLVM

[David B. <dav...@ya...>]

To All,
 
I was wondering if someone has looked in the use of the LLVM to be able to generate full featured python into synthesizable VHDL with simulation support of course ??  
 
I STRONGLY BELIEVE YOU GUYS NEED TO LOOK AT LLVM for greatly enhancing MyHDL to support a greater domain of the python language to support synthesizable designs and testbench support.  
 
David Blubaugh