Re: [myhdl-list] [PATCH] timezone in date in emitting HDL comment

[Christopher F. <chr...@gm...>]

On 1/8/13 8:08 PM, KISHIMOTO, Makoto wrote:
> Hello,
>
> I propose patch to print timezone in date in emitting HDL comment.


I think, in general this is a reasonable addition.  We
might want to formalize it a little and add a function
attribute for the time format (similar to the header
message).  If it is decided the common strftime format
can be used, the proposed can be used as the default
and add a function attribute so it can be customized.

    toVerilog.strftime = "%H"
    toVHDL.strftime = "%H"

I don't know if we want a limit on the number of
function attributes for customizing the conversion.
Currently, the following exist:

    toV*.name
    toV*.header
    toV*.no_myhdl_header
    toV*.timescale

Additional toVHDL attributes
    toVHDL.architecture
    toVHDL.component_declarations
    toVHDL.library
    toVHDL.no_myhdl_package

(some verilog attributes that show up in the 0.8-dev
that I am not familiar with)
    toVerilog.prefer_blocking_assignments
    toVerilog.radix
    toVerilog.standard

And the following have been proposed additions:

    toV*.strftime : Time format to be printed
    toV*.disable_signal_init : don't initialize signals
       when and if initialize signals implemented.
    toV*.enable_list_init : create the code for list
       of signals init.

The last two have been part of the RAM/ROM discussions.
To make it a little more flexible, I propose we use
the strftime pattern proposed as the default and add
a function attribute so it can be customized.

Regards,
Chris

>
> diff -ur myhdl-0.7.ORG/myhdl/conversion/_toVHDL.py myhdl-0.7/myhdl/conversion/_toVHDL.py
> --- myhdl-0.7.ORG/myhdl/conversion/_toVHDL.py	2010-10-15 02:58:48.000000000 +0900
> +++ myhdl-0.7/myhdl/conversion/_toVHDL.py	2013-01-07 16:27:12.000000000 +0900
> @@ -27,7 +27,7 @@
>   import math
>
>   import inspect
> -from datetime import datetime
> +import time
>   #import compiler
>   #from compiler import ast as astNode
>   import ast
> @@ -197,7 +197,7 @@
>   def _writeFileHeader(f, fn):
>       vars = dict(filename=fn,
>                   version=myhdl.__version__,
> -                date=datetime.today().ctime()
> +                date=time.strftime("%a %b %d %H:%M:%S %Y %Z")
>                   )
>       if not toVHDL.no_myhdl_header:
>           print >> f, string.Template(myhdl_header).substitute(vars)
> diff -ur myhdl-0.7.ORG/myhdl/conversion/_toVerilog.py myhdl-0.7/myhdl/conversion/_toVerilog.py
> --- myhdl-0.7.ORG/myhdl/conversion/_toVerilog.py	2010-10-15 02:58:48.000000000 +0900
> +++ myhdl-0.7/myhdl/conversion/_toVerilog.py	2013-01-07 16:27:44.000000000 +0900
> @@ -27,7 +27,7 @@
>   import math
>   import traceback
>   import inspect
> -from datetime import datetime
> +import time
>   import compiler
>   # from compiler import ast as astNode
>   import ast
> @@ -189,7 +189,7 @@
>   def _writeFileHeader(f, fn, ts):
>       vars = dict(filename=fn,
>                   version=myhdl.__version__,
> -                date=datetime.today().ctime()
> +                date=time.strftime("%a %b %d %H:%M:%S %Y %Z")
>                   )
>       if not toVerilog.no_myhdl_header:
>           print >> f, string.Template(myhdl_header).substitute(vars)
>
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