Re: [myhdl-list] VHDL Cosim Initial Thoughts

[Daryl W. <dw...@ou...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

> 
> On 1/4/13 2:55 PM, Daryl Wasden wrote:
<snip> 
> This sounds reasonable, instead of the $to_myhdl and
> $from_myhdl task (stubs to the VPI code) you can have
> equivalent VHDL processes.
> 
> I believe one of the items the FLI interface will need
> to support is getting a list of the signals from the
> VHDL simulator.  Resolving the signal interface from
> the MyHDL side to the VHDL simulator side, maybe a
> little tricky.  It might be simplified with the automatic
> generation of the VHDL processes?

It would be possible and easy to use a VHDL process to 
accomplish this with a wait statement terminating it, 
but I feel that may involve more work for the end user... 
However, I have settled on a different route that reads 
the port list of the module and if a signal is "in" it 
is used to populate the to_myhdl signals and if it is 
"out" it is used to populate the from_myhdl signals. This 
all occurs during initialization (right after elaboration 
has finished in ModelSim). I like this solution so far, 
but it will always be easy to go back to the approach that 
resembles the VPI Cosimulation approach more closely if 
desired (though it should appear the same from Python's
point-of-view). 

My view of how the VHDL Cosimulation is (only) slightly 
different from the Verilog Cosimulation. 

There will be a MyHDL top-level object containing the
testbench code as well as instantiations of any MyHDL
modules that will be used in the test. The simulator is
invoked with the Cosimulation() except that the arguments
that define the ports (by passing them to $to_myhdl and
$from_myhdl) are not required. These are instead defined
in the port list of a VHDL module that I am currently 
calling MyHDL_bridge and it is found in MyHDL_bridge.vhd.
This module is defined with the "foreign" attribute in 
its architecture and as such calls the C code that sets 
up the VHDL-side. There is also a top_level.vhd file 
that instantiates the MyHDL_bridge module as well as 
any VHDL modules that are used in the cosimulation and 
connects the ports from the MyHDL bridge to the 
instantiated modules. That's the track that I am 
currently pursuing...

> > Also, I haven't yet figured out how to deal with delays...
> I am not sure what you are asking or not understanding
> here? 

Sorry, I wasn't clear before. I meant to say I'm not sure 
how the C-side of the cosimulation knows that it needs to 
look for a delay. It looks like it is a well-defined 
ordering (it reads it in the read_only_callback shortly 
after sending the current HDL-state of the the signals to 
the MyHDL-side). Maybe this is due to the fact that delays 
are only allowed on the MyHDL-side, so a future event must 
be scheduled after all signals have settled? That's just a 
guess. If so, then I have found the way in FLI using a 
prioritized process (it should occur at exactly the same 
time as the read only callback does). Only one 
process/function is required in C, so I have to test to 
see if I am on a delta cycle iteration (at the same time 
step) or the first iteration at the current simulation 
time. Basically, all three of the call backs from the VPI 
method are collapsed into a single function in the FLI 
method. I haven't decided if this is going to be a 
problem yet... But I don't think so.

Anyway, like I said, I'm fairly confident I can resolve
this even if I'm wrong at the moment on exactly why it
works in the current implementation, but if it doesn't
work for the reasons I stated, it may take me some time
to figure out why and resolve it. But I will...

> > I am opting to subclass Cosimulation as CosimulationWithSockets.
> I think this sounds like a good idea and as you state
> might be a better option for other platforms (i.e. windows).
> I don't know enough about pipes or sockets to know if there
> are any issues.  My guess, is there should not be issues,
> but possibly performance?

I'm trying to have some preliminary code executing a 
cosimulation with Icarus Verilog and the old tests in 
the cosimulation directory using the socket-based 
communication in the next day or so, so I'll update 
this thread then with my findings. Hopefully, it will 
be a positive experience.
 
> The small consensus seem to support Modelsim as the most
> popular simulator for VHDL (obviously it would be nice to
> have an open-source option but it doesn't look like that
> is possible).  I don't recall anyone else stating another
> simulator (Aldec, ncsim, , etc)

There may be a way to do it using GHDL actually. GHDL does
support the VHPI for subprograms... I think with some 
creativity it might be possible to adopt an approach 
that would work... But it wouldn't be straightforward,
that's why I'm trying to get the FLI working. I want to 
start using MyHDL with VHDL as soon as I can...

Thanks for the responses,
Daryl