Re: [myhdl-list] VHDL Cosim Initial Thoughts

[Christopher F. <chr...@gm...>]

On 1/4/13 2:55 PM, Daryl Wasden wrote:
> Okay, I have read through _Cosimulation.py, _Simulation.py, and myhdl_vpi.c, and
> Jan's description here: http://www.myhdl.org/doc/0.7/manual/cosimulation.html
>
> I think I have a grasp on what the Verilog simulator is doing during
> cosimulation: Basically, run the simulation, schedule a callback that occurs
> when all signals are in steady-state, make successive callbacks to simulate
> Delta cycles from VHDL, and use delay callbacks to make sure the simulation
> times match up. At least if I'm interpreting everything correctly...

Sounds like the gist of it, I will have to review as a
refresher and see if any main points are not being
considered.

>
> I don't think this exact method will work with the ModelSim Foreign Language
> Interface (FLI) since it appears to me that some of these call backs are
> missing. However, I do see an easier/compatible option I think...
>
> My thoughts: The FLI allows one to register a VHDL process, create signals,
> assign a sensitivity list to the process, and read/drive signals from C. My plan
> (barring any problems in my interpretation so far) is to programmatically create
> a "MyHDL" process in the simulator with all of the from_myhdl signals in its
> sensitivity list, and read all of the output to_myhdl signals whenever this
> process is triggered and send them back to the Cosimulation object. These may be
> defined in the VHDL interface file somehow or else creating using FLI... I'm
> still working out details there.

This sounds reasonable, instead of the $to_myhdl and
$from_myhdl task (stubs to the VPI code) you can have
equivalent VHDL processes.

I believe one of the items the FLI interface will need
to support is getting a list of the signals from the
VHDL simulator.  Resolving the signal interface from
the MyHDL side to the VHDL simulator side, maybe a
little tricky.  It might be simplified with the automatic
generation of the VHDL processes?

>
> Also, I haven't yet figured out how to deal with delays from the MyHDL testbench
> (which will be important for sure)... But I'm sure I will find a way soon.

I am not sure what you are asking or not understanding
here?  The standard way to "delay" in a testbench is

       def testbench()
          ...
          @instance
          def tb_stimulus():
              yield delay(10)

The above will delay for 10 simulation cycles.
>
> In addition, I am opting to subclass Cosimulation as CosimulationWithSockets.
> This would override the methods of Cosimulation and modify them to implement
> their interprocess communication through network sockets instead of the pipes
> that are used now. This would allow the interprocess communication to occur over
> a network (letting me work on my laptop while running the simulation on a server
> for example). Also, it adds local cosimulation functionality to windows (via
> localhost) without Cygwin (with some performance loss maybe). It should work
> equally well (with appropriate preprocessing directives) under Windows,
> Unix/Linux, or Mac OS X. I've done some preliminary testing connecting python
> code to C code using sockets. So it looks like this is feasible.

I think this sounds like a good idea and as you state
might be a better option for other platforms (i.e. windows).
I don't know enough about pipes or sockets to know if there
are any issues.  My guess, is there should not be issues,
but possibly performance?

>
> Any comments/questions/ideas are welcome. Thoughts and feedback on pros/cons of
> this approach would be greatly appreciated. Also, would this be useful for
> anyone else? If so, I'll post code once I have it working.

The small consensus seem to support Modelsim as the most
popular simulator for VHDL (obviously it would be nice to
have an open-source option but it doesn't look like that
is possible).  I don't recall anyone else stating another
simulator (Aldec, ncsim, , etc)

Regards,
Chris

>
> Once I have something that I believe is working, I'll test it by running the
> tests in the cosimulation directory (appropriately modified and using VHDL).
>
> Thanks for any feedback,
> Daryl
>
>
>
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