Re: [myhdl-list] Signal initialization

[Christopher F. <chr...@gm...>]

On 12/3/12 3:56 AM, Martin Thompson wrote:
> Angel Ezquerra <ang...@gm...> writes:
>
>> I was thinking of the behavior of the code when some signals are still
>> not initialized (i.e. undefined). The "stdl" and "bool" functions on
>> the pck_myhdl helper file use comparions with 0 and '1'
>> (respectively), and I am unsure as to how those will behave when fed
>> and undefined value:
>>
>>      function stdl (arg: integer) return std_logic is
>>      begin
>>          if arg /= 0 then
>>              return '1';
>>          else
>>              return '0';
>>          end if;
>>      end function stdl;
>
> You can't feed that an uninitalised value - it takes an integer :)
>
>>
>>      function bool (arg: std_logic) return boolean is
>>      begin
>>          return arg = '1';
>>      end function bool;
>>
>
> That'll return false for everything other than a '1', so a 'U' (and
> 'X', and 'Z'...).  Also, 'H' will return false which may or may not be
> regarded as a bug?
>
>> In addition I wonder if this will not make VHDL simulations slower
>> unnecessarily? I don't know... it just feels a bit unnecessary.
>>
>
> I imagine this is a case of correctness-first, performance later (and
> only if a proven benefit can be demonstrated)

I would say, this is exactly the case.  Focus on correctness of the 
converted HDL and not the converted HDL simulation speed.

The design goal is that VHDL/Verilog (target HDLs) are intended to be an 
intermediate formats and mainly used by the tools.  Although you would 
need to verify the converted HDL has the same behavior as the MyHDL 
description it is common that the MyHDL simulation would run more often 
than the converted HDL simulation.

Regards,
Chris