Re: [myhdl-list] Signal initialization

[Christopher F. <chr...@gm...>]

<snip>
>>
>> Based on my recollection it has been agreed upon that using initialized
>> signals/variables in the converted HDL (both VHDL and Verilog) is
>> desired to avoid MyHDL simulation mismatch with the target HDL.  But in
>> some cases it was disabled because it was not supported by FPGA vendor
>> synthesis tools.  This was true with Verilog and Altera Quartus but my
>> guess is that the synthesis tools probably support the VHDL
>> initialization fine (have never ran into an issue).
>>
>> The initialization might have been disable because the converted Verilog
>> and VHDL would differ (a guess)?
>>
>> I quick test and the modified line 306 in _toVHDL.py in the latest
>> 0.8dev to:
>>
>>      print >> f, "signal %s: %s%s := %s;" % (s._name, p, r, str(s._val))
>
> I'll give this a try.
> Interestingly, the lines right above the one you modified are as follows:
>
>      # the following line implements initial value assignments
>      # print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val))
>
> They are commented, but they seem to be intended to do what we want
> although  the code looks different enough that I am not sure this
> would work with the current version of _toVHDL (there is no explicit
> "signal", it uses _driven() and converts the value to an int rather
> than calling str() on it).

I am not sure what the comment line is but I do not believe it is 
correct (at least not for VHDL).  Someone would have to review the 
history to see

>
> That being said, I don't really know about Verilog, but default signal
> values are part of the VHDL standard syntax. I don't understand why
> would we not support it. IMHO it is _very_  surprising to have the
> convertor ignore the init value that you explicitly set on the python
> code, when the VHDL standard supports such a thing.

Defaults are part of the Verilog standard as well.  For Verilog, at 
least a couple years ago, Altera Quartus synthesis did not support the 
syntax.  That is not the case any more.  And I doubt it was ever the 
case for VHDL.

>
> Do you know if there are any plants to add this to 0.8? Maybe Jan
> could give his opinion on this?
>

No, I am not aware of any explicit plans for init value in 0.8.


Regards,
Chris