Re: [myhdl-list] Signal initialization

[Christopher F. <chr...@gm...>]

On 11/30/12 6:20 AM, Angel Ezquerra wrote:
> Hi,
>
> I have a question that probably is quite basic, but I don't seem to
> get it right and I have not found an answer on the documentation
> (perhaps I missed it though).
>
> I am making a simple MyHDL module, and in it I define several
> std_logic signals as follows:
>
>     captured, demet, sync1, sync2 = [Signal(bool(0)) for n in range(4)]
>
> I expected these to be converted into the following VHDL:
>
>      signal captured: std_logic := '0';
>      signal demet: std_logic := '0';
>      signal sync2: std_logic := '0';
>      signal sync1: std_logic := '0';
>
> Instead I get:
>
>      signal demet: std_logic;
>      signal sync2: std_logic;
>      signal sync1: std_logic;
>      signal captured: std_logic;

Based on my recollection it has been agreed upon that using initialized 
signals/variables in the converted HDL (both VHDL and Verilog) is 
desired to avoid MyHDL simulation mismatch with the target HDL.  But in 
some cases it was disabled because it was not supported by FPGA vendor 
synthesis tools.  This was true with Verilog and Altera Quartus but my 
guess is that the synthesis tools probably support the VHDL 
initialization fine (have never ran into an issue).

The initialization might have been disable because the converted Verilog 
and VHDL would differ (a guess)?

I quick test and the modified line 306 in _toVHDL.py in the latest 
0.8dev to:

    print >> f, "signal %s: %s%s := %s;" % (s._name, p, r, str(s._val))

This will add the initialization to the locally declared signals.  I 
didn't think about this much, just tried a hack.  Here is an example.

~~~ [MyHDL] ~~~
    from myhdl import *

    def goo(clock, reset, x, y, z, zz):
        b = Signal(intbv(5, min=-13, max=22))
        bb = Signal(intbv(5, min=z.min, max=z.max))
        @always_seq(clock.posedge, reset=reset)
        def hdl():
            z.next = (x - y) + b
            bb.next = z - (2*b)
            zz.next = z + bb
        return hdl

    clock = Signal(bool(0))
    reset = ResetSignal(bool(0), active=0, async=False)
    x,y,z = (Signal(intbv(3, min=-4, max=7)),
             Signal(intbv(0, min=-8, max=8)),
             Signal(intbv(-67, min=-80, max=80)))
    zz = Signal(intbv(-37, min=-80, max=80))
    toVHDL(goo, clock, reset, x, y, z, zz)

~~~ [VHDL] ~~~

    architecture MyHDL of goo is

    signal b: signed (5 downto 0);
    signal bb: signed (7 downto 0) := 5;

    begin

    b <= to_signed(5, 6);

    GOO_HDL: process (clock) is
    begin
        if rising_edge(clock) then
            if (reset = '0') then
                z <= 10111101;
                zz <= 11011011;
                bb <= 00000101;
            else
                z <= ((resize(x, 8) - y) + b);
                bb <= resize(z - (2 * b), 8);
                zz <= (z + bb);
            end if;
        end if;
    end process GOO_HDL;

    end architecture MyHDL;


>
> Other than the order not being the same, which I guess is unavoidable,
> the values are not being initialized to zero as I expected (which
> causes my simulation to fail).

Why does it cause your simulation to fail?

>
> Additionally, I see in the converted code that the following code:
>
>      captured.next = not demet
>
> which uses the signals declared above is converted into:
>
>      captured <= stdl((not bool(demet)));
>
> rather than into:
>
>      captured <= not demet;
>
> The conversion from std_logic to bool and then back to std_logic is
> unnecessary... I guess it probably does not matter except perhaps
> during simulation before the reset, but maybe it can cause some
> problems in simulation as well?

I can't think of any simulation issues that may occur?  Simply cast 
std_logic to a bool perform the not on a bool then cast back to a std_logic?

Regards,
Chris