[myhdl-list] Signal initialization

[Angel E. <ang...@gm...>]

Hi,

I have a question that probably is quite basic, but I don't seem to
get it right and I have not found an answer on the documentation
(perhaps I missed it though).

I am making a simple MyHDL module, and in it I define several
std_logic signals as follows:

   captured, demet, sync1, sync2 = [Signal(bool(0)) for n in range(4)]

I expected these to be converted into the following VHDL:

    signal captured: std_logic := '0';
    signal demet: std_logic := '0';
    signal sync2: std_logic := '0';
    signal sync1: std_logic := '0';

Instead I get:

    signal demet: std_logic;
    signal sync2: std_logic;
    signal sync1: std_logic;
    signal captured: std_logic;

Other than the order not being the same, which I guess is unavoidable,
the values are not being initialized to zero as I expected (which
causes my simulation to fail).

Additionally, I see in the converted code that the following code:

    captured.next = not demet

which uses the signals declared above is converted into:

    captured <= stdl((not bool(demet)));

rather than into:

    captured <= not demet;

The conversion from std_logic to bool and then back to std_logic is
unnecessary... I guess it probably does not matter except perhaps
during simulation before the reset, but maybe it can cause some
problems in simulation as well?

Thanks,

Angel