Re: [myhdl-list] Meaning of the apostrophe that MyHDL adds after VHDL casts when using "concat"

[Martin T. <mar...@tr...>]

Angel Ezquerra <ang...@gm...> writes:

> ~~~
>     s_output <= unsigned'(s_input3 & s_input3);
> ~~~
>
> Which synthesizes fine and without warning.
>
> What does the apostrophe mean?
>

This came up on comp.lang.vhdl recently:
https://groups.google.com/d/msg/comp.lang.vhdl/C5ZaMbKujGo/fpXyOSFb5gEJ

Andy says it very well:

> type_name'(expression) is called a qualified expression. It explicitly
> tells the compiler that the expression IS of type type_name. This is
> used, as in your example, when the result of a function/operation is
> ambiguous. These are often confusing, since such an ambigous expression
> will work if assigned directly to an object or associated with a port
> (which always has a defined type). Ambiguous expressions often involve
> literal expressions like (7 downto 0 => '0'), in contexts where there
> are multiple available types that fit the literal expression. No type
> conversion is involved in a qualified expression.
> 
> type_name(expression) is a built-in type conversion function that
> automatically exists between closely related types (aggregates whose
> elements are of the same base type). This is as close to a "cast" as
> vhdl gets.
> 
> conversion_function_name(expression) is an explicit type conversion
> function that has to be written and compiled, and can convert between
> any two types.

Cheers,
Martin

-- 
mar...@tr... 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
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