[myhdl-list] Meaning of the apostrophe that MyHDL adds after VHDL casts when using "concat"

[Angel E. <ang...@gm...>]

Hi,

this may be a very basic VHDL question but is something I have never
seen before.

Looking at the VHDL code that MyHDL generates I noticed that when
using "concat" MyHDL adds an apostrophe (') between the casting
functions (e.g. unsigned or signed) and the parenthesis that contain
the actual signal concatenation.

For example, given two variables defined as follows in MyHDL:

~~~
    s_input = Signal(intbv(0)[16:])
    s_output = Signal(intbv(0)[32:])
~~~

The following MyHDL code, when placed on an @always block:

~~~
    s_output.next = concat(s_input, s_input)
~~~

becomes the following VHDL:

~~~
    s_output <= unsigned'(s_input3 & s_input3);
~~~

Which synthesizes fine and without warning.

What does the apostrophe mean?

Thanks!

Angel