[myhdl-list] [PATCH 2 of 2 RFC] toVHDL: add support for negative indexes

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1350086923 -7200
# Branch 0.8-dev
# Node ID 1a024c51a10d48b9de7e5d0d3886e3498c4dcfbb
# Parent  c641c1ed333d6d03d9cee4a63df5111fe98574c8
toVHDL: add support for negative indexes

This is _very_ rough.

This patch tries to detect negative indexes and converts them into indexes
relative to the highest bit position (with -1 corresponding to the highest bit).

This probably breaks all sorts of things since it does not check if the index
is an integer or not, and the way it updates the slice node is probably wrong
as well.

However, the following simple test case converts fine with this patch:
~~~
#!/usr/env python
from myhdl import *

def test_module(rst, clk):
    '''This block generates the radio frame synchronization signal'''
    s_output = Signal(intbv(0)[16:])
    s_input = Signal(intbv(0)[16:])

    @always(clk.posedge, rst.posedge)
    def p_process():
        if rst == 1:
            s_input[-1] = 1
            s_output.next = s_input
        else:
            pass


    return instances()

clk, rst = [Signal(bool()) for n in range(2)]

if __name__ == '__main__':
    sync_inst = toVHDL(test_module3, rst, clk)
~~~

diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -1293,6 +1293,12 @@
         self.visit(node.value)
         self.write("(")
         #assert len(node.subs) == 1
+        if node.slice.value.value < 0:
+            # convert negative indexes into indexes from the MSB
+            newindex = node.value.obj._nrbits + node.slice.value.value
+            node.slice.value = newindex
+            node.slice.value.n = newindex
+            node.slice.value.value = newindex
         self.visit(node.slice.value)
         self.write(")")
         self.write(suf)