Re: [myhdl-list] Problems converting an integer assignment into VHDL
Brought to you by:
jandecaluwe
From: Norbo <Nor...@gm...> - 2012-10-11 18:52:58
|
> Yes, it seems that using an intermediate variable to get the value of > s_my_signal.max works fine and is an easy work around. > > That being said, is this technique to set a signal to all '1' the one > you guys would use? Or is there a more idiomatic way? I actually never came across this in that way before. Thanks for pointing it out, so i didn't have to run into it again!. When i did something similar the configuration looked somehow like this: def somefunc(clk,in,out,sss,BIT_WIDTH=8): sig1=Signal(intbv(0)[BIT_WIDTH:]) @always(clk.posedge) def readbla(): sig1.next=(2**BIT_WIDTH)-1 well and the other possibilities would be: sig1=Signal(intbv(0)[8:]) const_AllOne=(2**sig1._nrbits)-1 @always(clk.posedge) def readbla(): sig1.next=const_AllOne or the allready discussed quite similar one: sig1=Signal(intbv(0)[8:]) const_AllOne=sig1.max-1 @always(clk.posedge) def readbla(): sig1.next=const_AllOne iam not able to produce any other usefull way for this right now. But i actually also would prefer the direct use of the "signal.max". This seems to be at least somehow realated: http://sourceforge.net/mailarchive/message.php?msg_id=29738279 MEP would be the next step right?. greetings Norbo |