[myhdl-list] [PATCH V2] toVHDL: add signal attribute support

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349884148 -7200
# Branch 0.8-dev
# Node ID 6f6571dbd495f197531f0406763ff10e4ce3b3ee
# Parent  58ac2e97c7efbe7e3c9784b8ac25218daa056e40
toVHDL: add signal attribute support

This adds a new setAttribute() method to the Signal type, which lets the user
set attributes that will be set on the VHDL output.

In order to make it easy to avoid declaring the same attribute more than once,
all the signal attributes are written together, after all signal declarations.

The setAttribute() Signal method has the following interface:

    Signal.setAttribute(attribute_name, attribute_value, [attribute_type])

If attribute_type is not set the function will try to guess it (it will be set
to 'string' if the attribute_value is a string, or to integer otherwise).

For example:

    my_signal.setAttribute('test_int_attrib1', 11, 'integer')
    my_signal.setAttribute('test_int_attrib2', -234)
    my_signal.setAttribute('test_string_attrib1', 'test_value1')
    my_signal.setAttribute('test_string_attrib2', 'test_value2', 'string')

Will give the following VHDL output:

    signal my_signal: unsigned(15 downto 0);
    attribute ram_style : string;
    attribute ram_style of my_signal: signal is "block";

    attribute test_int_attrib1 : integer;
    attribute test_int_attrib1 of s_input: signal is 11;
    attribute test_int_attrib2 : integer;
    attribute test_int_attrib2 of s_input: signal is -234;
    attribute test_string_attrib1 : string;
    attribute test_string_attrib1 of s_input: signal is "test_value1";
    attribute test_string_attrib2 : string;
    attribute test_string_attrib2 of s_input: signal is "test_value2";

Currently the attributes are set in alphabetical order. Using a sorted dict to
store the attributes could let us keep their setting order.

An example use case is to be able to tell to the Xilinx XST synthesizer that a
memory must be implemented as Block RAM.

This does not add support for Verilog output.

diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py
--- a/myhdl/_Signal.py
+++ b/myhdl/_Signal.py
@@ -107,10 +107,10 @@
                  '_code', '_tracing', '_nrbits', '_checkVal', 
                  '_setNextVal', '_copyVal2Next', '_printVcd', 
                  '_driven' ,'_read', '_name', '_used', '_inList',
-                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs'
+                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs',
+                 'setAttribute', '_attributes'
                 )
 
-
     def __init__(self, val=None):
         """ Construct a signal.
 
@@ -118,6 +118,7 @@
         
         """
         self._init = deepcopy(val)
+        self._attributes = {}
         self._val = deepcopy(val)
         self._next = deepcopy(val)
         self._min = self._max = None
@@ -300,6 +301,9 @@
     def _printVcdVec(self):
         print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
 
+    def setAttribute(self, name, value, attribute_type=None):
+        self._attributes[name] = (value, attribute_type)
+
     ### use call interface for shadow signals ###
     def __call__(self, left, right=None):
         s = _SliceSignal(self, left, right)
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -286,6 +286,22 @@
 
 constwires = []
 
+def _writeAttributes(f, siglist):
+    declared_attributes = set()
+    for s in siglist:
+        for name in sorted(s._attributes):
+            value, attribute_type = s._attributes[name]
+            if attribute_type is None:
+                # consider all attributes strings by default
+                attribute_type = 'string'
+                if isinstance(value, int):
+                    attribute_type = 'integer'
+            if name not in declared_attributes:
+                declared_attributes.add(name)
+                print >> f, "    attribute %s : %s;" % (name, attribute_type)
+            if attribute_type == 'string':
+                value = '"%s"' % value
+            print >> f, "    attribute %s of %s: signal is %s;" % (name, s._name, value)
 
 def _writeSigDecls(f, intf, siglist, memlist):
     del constwires[:]
@@ -329,6 +345,9 @@
         t = "t_array_%s" % m.name
         print >> f, "    type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
         print >> f, "    signal %s: %s;" % (m.name, t)
+
+    _writeAttributes(f, siglist + memlist)
+
     print >> f
 
 def _writeCompDecls(f,  compDecls):