Re: [myhdl-list] Problems using signal slices and variables
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From: Angel E. <ang...@gm...> - 2012-10-11 16:18:09
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On Thu, Oct 11, 2012 at 5:45 PM, Christopher Felton <chr...@gm...> wrote: > On 10/11/2012 6:10 AM, Angel Ezquerra wrote: >> Hi, >> >> I'm playing around with concatenating and slicing signals in MyHDL. >> I'm having some trouble with slicing in particular. >> >> I am having a hard time predicting what MyHDL will do when the code is >> converted to VHDL, and sometimes what I get seems wrong (or at least >> it is not what I expected). >> >> In particular, I've got the following code (note that the code has no >> purpose other than testing how MyHDL works): >> >> s_input = Signal(intbv(0)[59:]) >> s_output = Signal(intbv(0)[59:]) >> s_slice = s_input(15, 0) # Use a shadow signal >> >> @always(clk.posedge, rst.posedge) >> def p_process(): >> if rst == 1: >> max_value = s_input.max - 1 >> s_input.next = max_value >> var_test = s_input[15:0] # I expect var_test to be a >> variable of range 14 downto 0, i.e. size 15 >> s_output.next = concat(s_input[15:0], s_input[30:15], >> s_input) # Total size: 15 + 15 + 30 = 60 >> s_output.next = concat(s_slice, s_input[30:15], s_input) >> # Total size: 15 + 15 + 30 = 60 >> s_output.next = concat(var_test, s_input[30:15], s_input) >> # Total size: 15 + 15 + 30 = 60 >> else: >> pass >> > > Not following your math for the last concat > > > s_output.next = concat(var_test, s_input[30:15], s_input) > > var_test = 15 (14 downto 0) > s_input[30:15] = 15 (29 downto 15 ) > s_input = 59 (58 downto 0) > > trying to concat 89. > > In [63]: s_input = Signal(intbv(0)[59:]) > ...: s_output = Signal(intbv(0)[59:]) > ...: var_test = s_input[15:0] > ...: len(concat(var_test, s_input[30:15], s_input)) > ...: > Out[63]: 89 > > .chris Sorry Chris, I made a typo on my example. s_input is 30 bits long, not 60, i.e. s_input = Signal(intbv(0)[30:]) The problem is that var_test is 30 bits long rather than 15 as I expected. Cheers, Angel |