Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Christopher F. <chr...@gm...>]

On 10/11/2012 9:52 AM, Christopher Felton wrote:
> <snip>
>>
>>
>> so it turns out that the converter doesn't recognise the "s_my_signal.max"
>> as an const integer, but instead as a signal.
>> This seems to be also the case for the simulator.
>> e.g:  In a combinatorical process this leads to a -> combinatorical loop
>> error, when there is actually none.
>>
>>
>>        sigTest=Signal(intbv(0)[4:])
>>        @always_comb
>>        def comb_setConst():
>>          sigTest.next=int(sigTest.max)-1
>>
>>
>
> Yes, in a generator an "buried" constant can't be used.
> The converter will not walk down the structure (list,
> dict, class, etc) to find the value.  On the right hand
> side the only valid types are for conversion:
>
>       int, long, intbv, bool
>

I didn't mention the special case of tuple of ints and
list of signals.  These two cases a structure can be
used on the right hand side.

.chris