Re: [myhdl-list] intbv connections to/from instance array
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Re: [myhdl-list] intbv connections to/from instance array
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From: Michael B. <ms...@gm...> - 2012-10-11 13:39:28
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Thanks a lot, Chris, that works! Yes, I already fell into the trap of trying using lists at the top level. I was hoping to use it to model an array of N std_logic_vectors in VHDL. That led me to this simpler bit array <-> intbv problem. Based on your solution, I created two simple functions to make the connections: intvb2bool and bool2intbv. The program is attached. It is a little unsatisfying to have so much code for a wire, but I suspect that's why the shadow_signals were created. I appreciate the help with my noob questions as I become more familiar with the nuances of this cool tool. Mike On Wed, Oct 10, 2012 at 3:59 PM, Christopher Felton <chr...@gm...> wrote: > On 10/10/2012 12:07 PM, Michael Babst wrote: >> What is the preferred method to connect the intbv signals to/from >> an instance array. In the example code below, the connections to >> dvec and qvec are not made in the generated VHDL. I have been >> unable to get shadow signals or signal lists to work in this >> scenario. >> >> Thank you! >> >> >> from myhdl import * >> >> N = 8 >> >> def reg(d,q,en,clk,arstn): >> @always(clk.posedge, arstn.negedge) >> def regLogic(): >> if arstn == 0: >> q.next = 0 >> else: >> if en: >> q.next = d >> return regLogic >> >> >> def regArray(dvec,qvec,en,clk,arstn): >> >> u_reg = [None for i in range(N)] >> >> for i in range(N): >> u_reg[i] = reg(dvec[i],qvec[i],en,clk,arstn) >> >> return u_reg >> >> >> en = Signal(bool(0)) >> clk, arstn = [Signal(bool()) for i in range(2)] >> >> dvec = Signal(intbv(0)[N:]) >> qvec = Signal(intbv(0)[N:]) >> >> toVHDL(regArray,dvec,qvec,en,clk,arstn) >> > > > Hmmm, I had some difficulty getting the shadow signal > method to work, as well. The following is my list-of-signals > (LoS) version. The LoS can only be used locally, can't > be passed as a top-level port. > > In [49]: from myhdl import * > ...: > ...: N = 8 > ...: > ...: def reg(d,q,en,clk,arstn): > ...: @always(clk.posedge, arstn.negedge) > ...: def regLogic(): > ...: if arstn == 0: > ...: q.next = 0 > ...: else: > ...: if en: > ...: q.next = d > ...: return regLogic > ...: > ...: > ...: def regArray(dvec,qvec,en,clk,arstn): > ...: > ...: u_reg = [None for i in range(N)] > ...: d = [Signal(bool(0)) for ii in range(N)] > ...: q = [Signal(bool(0)) for ii in range(N)] > ...: > ...: @always_comb > ...: def hdl_assigns(): > ...: for jj in range(N): > ...: d[jj].next = dvec[jj] > ...: qvec.next[jj] = q[jj] > ...: > ...: for i in range(N): > ...: u_reg[i] = reg(d[i],q[i],en,clk,arstn) > ...: > ...: return hdl_assigns, u_reg > ...: > ...: > ...: en = Signal(bool(0)) > ...: clk, arstn = [Signal(bool()) for i in range(2)] > ...: > ...: dvec = Signal(intbv(0)[N:]) > ...: qvec = Signal(intbv(0)[N:]) > ...: > ...: toVHDL(regArray,dvec,qvec,en,clk,arstn) > > > Manual reference is here: > http://www.myhdl.org/doc/0.7/manual/modeling.html#inferring-the-list-of-instances > > Regards, > Chris > > >> ------------------------------------------------------------------------------ >> Don't let slow site performance ruin your business. Deploy New Relic APM >> Deploy New Relic app performance management and know exactly >> what is happening inside your Ruby, Python, PHP, Java, and .NET app >> Try New Relic at no cost today and get our sweet Data Nerd shirt too! >> http://p.sf.net/sfu/newrelic-dev2dev >> > > > > ------------------------------------------------------------------------------ > Don't let slow site performance ruin your business. Deploy New Relic APM > Deploy New Relic app performance management and know exactly > what is happening inside your Ruby, Python, PHP, Java, and .NET app > Try New Relic at no cost today and get our sweet Data Nerd shirt too! > http://p.sf.net/sfu/newrelic-dev2dev > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
