Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Angel E. <ang...@gm...>]

Benoit,

thank you for your comment. I think your advice is sensible. However I
have two purposes with this:

1. Learn the nits of the language. What can be done and what cannot be done
2. See how I can use MyHDL on a project that already uses VHDL

#1 is the reason why I am trying to convert an existing module. I know
what it must do so it is easy to try the current behavior. I purposely
tried to directly translate it, rather than coding it from scratch
just to see what VHDL constructs translate well to MyHDL and which do
not. I hope this will also teach which constructs are synthesizable
and which are not. My intention is to rewrite it again from scratch
once this intial learning phase is done.

Most importantly however, purpose #2 places several fundamental
limitations on how I can use the language. In particular I am bound to
use the interfaces that are provided to me by the rest of the modules
on our project, most of which I cannot control.

All our interfaces use std_logic_vectors and often these
std_logic_vectors group several fields (which are simply
concatenated). This is often quite low level (which I guess is common
when writing synthesizable VHDL code) and  forces me to work with and
"think in bits" even if that is not the natural level of abstraction
of MyHDL.

For example our current interfaces sometimes use the "all 1" value to
indicate that some data is invalid. My first approach to this in MyHDL
was to "forget about the bits" and set the value of that signal using
its max property (minus 1). However this does not work that well (as
discussed on another thread). This is exactly the kind of thing I am
trying to discover.

I think it would be much easier to follow your advice if I were to use
MyHDL on a project that were started from scratch. But unfortunately
that is not the case :-(

Cheers,

Angel


On Thu, Oct 11, 2012 at 1:48 PM, Ben <ben...@gm...> wrote:
> On Thu, Oct 11, 2012 at 12:06 PM, Angel Ezquerra
> <ang...@gm...> wrote:
>> That being said, is this technique to set a signal to all '1' the one
>> you guys would use? Or is there a more idiomatic way?
>>
>
> With all my respect, you are looking at it the wrong way.
>
> I know you are trying to 'translate' a module from VHDL to MyHDL, but
> you should understand that both language are far from being
> 'equivalent'. With MyHDL, you are climbing in the abstraction, and
> trying to write your MyHDL so that it looks like the VHDL can only
> produce poor code.
>
> Try to take some time, and think of the functionality of your module
> again, do that the MyHDL way, with all the power of Python, you could
> get some nice surprises. Your code should become simpler.
>
> I understand it's difficult at first to completely grasp the power of
> the tool you have at hand. You saw it running, it has some nice
> features, but where do they end ? I saw lately some nice examples with
> the signal containers for instance, especially the one that did not
> necessitate any modification of the MyHDL source code, support for it
> is there, simply because it's python.
>
> Your value of 111....111, what is it ? an invalid state ? an
> uninitialised state ? a valid one? Each of those answer has it's own
> way to write it. You should step up and forget about the 1 and the 0
> ...
>
> Hope this helps.
>
> Have fun coding !
> Benoît.