Re: [myhdl-list] Problems converting an integer assignment into VHDL

[Ben <ben...@gm...>]

On Thu, Oct 11, 2012 at 12:06 PM, Angel Ezquerra
<ang...@gm...> wrote:
> That being said, is this technique to set a signal to all '1' the one
> you guys would use? Or is there a more idiomatic way?
>

With all my respect, you are looking at it the wrong way.

I know you are trying to 'translate' a module from VHDL to MyHDL, but
you should understand that both language are far from being
'equivalent'. With MyHDL, you are climbing in the abstraction, and
trying to write your MyHDL so that it looks like the VHDL can only
produce poor code.

Try to take some time, and think of the functionality of your module
again, do that the MyHDL way, with all the power of Python, you could
get some nice surprises. Your code should become simpler.

I understand it's difficult at first to completely grasp the power of
the tool you have at hand. You saw it running, it has some nice
features, but where do they end ? I saw lately some nice examples with
the signal containers for instance, especially the one that did not
necessitate any modification of the MyHDL source code, support for it
is there, simply because it's python.

Your value of 111....111, what is it ? an invalid state ? an
uninitialised state ? a valid one? Each of those answer has it's own
way to write it. You should step up and forget about the 1 and the 0
...

Hope this helps.

Have fun coding !
Benoît.