[myhdl-list] Problems using signal slices and variables

[Angel E. <ang...@gm...>]

Hi,

I'm playing around with concatenating and slicing signals in MyHDL.
I'm having some trouble with slicing in particular.

I am having a hard time predicting what MyHDL will do when the code is
converted to VHDL, and sometimes what I get seems wrong (or at least
it is not what I expected).

In particular, I've got the following code (note that the code has no
purpose other than testing how MyHDL works):

    s_input = Signal(intbv(0)[59:])
    s_output = Signal(intbv(0)[59:])
    s_slice = s_input(15, 0) # Use a shadow signal

    @always(clk.posedge, rst.posedge)
    def p_process():
        if rst == 1:
            max_value = s_input.max - 1
            s_input.next = max_value
            var_test = s_input[15:0] # I expect var_test to be a
variable of range 14 downto 0, i.e. size 15
            s_output.next = concat(s_input[15:0], s_input[30:15],
s_input) # Total size: 15 + 15 + 30 = 60
            s_output.next = concat(s_slice, s_input[30:15], s_input)
# Total size: 15 + 15 + 30 = 60
            s_output.next = concat(var_test, s_input[30:15], s_input)
# Total size: 15 + 15 + 30 = 60
        else:
            pass

And I get:

TEST_MODULE_P_PROCESS: process (clk, rst) is
    variable max_value: integer;
    variable var_test: unsigned(29 downto 0);
begin
    if (rst = '1') then
        max_value := to_integer(1073741824 - 1);
        s_input <= to_unsigned(max_value, 30);
        var_test := resize(s_input(15-1 downto 0), 30);
        s_output <= unsigned'(s_input(15-1 downto 0) & s_input(30-1
downto 15) & s_input);
        s_output <= unsigned'(s_input(15-1 downto 0) & s_input(30-1
downto 15) & s_input);
        s_output <= unsigned'(var_test & s_input(30-1 downto 15) & s_input);
    elsif rising_edge(clk) then
        null;
    end if;
end process TEST_MODULE_P_PROCESS;

What I do not understand is why MyHDL makes var_test be of size 30,
which results in it using resize and then makes the last statement:

        s_output <= unsigned'(var_test & s_input(30-1 downto 15) & s_input);

appear to be wrong, since s_output has size 60, while var_test and
s_input have size 30. The total size above would be 30 + 15 + 30, i.e.
75.

I am getting this wrong?

Thanks,

Angel