[myhdl-list] Problems converting an integer assignment into VHDL

[Angel E. <ang...@gm...>]

Hi,

I got an issue with conversion to VHDL, where MyHDL seems to do the
wrong thing (although most likely it's me who is doing it wrong).

The problem is that MyHDL maps an integer assignment into an intbv
signal as a direct integer assignment in VHDL, instead of using a
to_unsigned conversion.

That is, I got a signal declared as follows:

    signal s_my_signal: unsigned(29 downto 0);

Then I do:

    s_my_signal.next = s_my_signal.max - 1

which in VHDL becomes:

    s_my_signal.next <= 1073741824 - 1;

Which is wrong. Instead I expected it to be:

    s_my_signal.next <= to_unsigned(1073741824 - 1, 30);

Or something of the sort.

I thought that I could fix the problem by doing:

    s_my_signal.next = intbv(1073741824.max)[len(s_2pps_counter):]

Which would be unnecessarily verbose (IMHO) but in fact it makes
matters worse, as it converts into:

    s_2pps_counter <= 1073741824(30-1 downto 0);

Is there something I'm doing wrong?

Additionally, is this the best way to initialize an unsigned signal to
all 1's? This is probably not in the "MyHDL style" but for now I'm
just trying to convert an existing VHDL module into MyHDL just to get
the feel of things.

Thanks,

Angel