[myhdl-list] intbv connections to/from instance array

[Michael B. <ms...@gm...>]

What is the preferred method to connect the intbv signals to/from
an instance array.  In the example code below, the connections to
dvec and qvec are not made in the generated VHDL.  I have been
unable to get shadow signals or signal lists to work in this
scenario.

Thank you!


from myhdl import *

N = 8

def reg(d,q,en,clk,arstn):
    @always(clk.posedge, arstn.negedge)
    def regLogic():
        if arstn == 0:
            q.next = 0
        else:
            if en:
                q.next = d
    return regLogic


def regArray(dvec,qvec,en,clk,arstn):

    u_reg = [None for i in range(N)]

    for i in range(N):
        u_reg[i]     = reg(dvec[i],qvec[i],en,clk,arstn)

    return u_reg


en         = Signal(bool(0))
clk, arstn = [Signal(bool()) for i in range(2)]

dvec       = Signal(intbv(0)[N:])
qvec       = Signal(intbv(0)[N:])

toVHDL(regArray,dvec,qvec,en,clk,arstn)