Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow
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Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow
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From: Angel E. <ang...@gm...> - 2012-10-10 16:35:22
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On Wed, Oct 10, 2012 at 6:09 PM, Christopher Felton <chr...@gm...> wrote: > On 10/10/2012 11:04 AM, Angel Ezquerra wrote: >> On Wed, Oct 10, 2012 at 5:56 PM, Christopher Felton >> <chr...@gm...> wrote: >>> On 10/10/2012 10:46 AM, Angel Ezquerra wrote: >>>> On Wed, Oct 10, 2012 at 2:25 PM, Christopher Felton >>>> <chr...@gm...> wrote: >>>>> <snip> >>>>>> >>>>>> >>>>>>>> Anyway, since this process seems easy to automate (I can't really >>>>>>>> tell, since I don't really understand it), the obvious question is why >>>>>>>> not make MyHDL itself automate it for us? That should put to rest the >>>>>>>> question of generating hierarchical VHDL or Verilog code which seems >>>>>>>> to crop up regularly on this list and on other online discussions >>>>>>>> about MyHDL! >>>>>>> >>>>>>> The obvious question is why someone interested in a >>>>>>> feature doesn't propose a MEP and a patch? >>>>>> >>>>>> That is a fair point. I am still "testing the waters" with MyHDL so to >>>>>> speak, so for now I am just raising the concerns that I come up with. >>>>>> >>>>>> I could try to write a MEP but first I'd like to see if there is some >>>>>> consensus that this could be a worthy idea (as I believe it is). Also, >>>>>> what would be the preferred way to indicate that a group of generators >>>>>> should be grouped into an entity and placed on their own file? >>>>>> >>>>>> For example, in the case that you described, imagine that you had had >>>>>> a magic wand that let you modify MyHDL in a way that you could have >>>>>> avoided all the manual work involved in solving your problem. How >>>>>> would you have liked to be able to tell MyHDL that you wanted to place >>>>>> "submodule" on its own file? >>>>>> >>>>>> Contributing a patch is another matter though. I am quite busy >>>>>> contributing to TortoiseHg at the moment and I don't know how complex >>>>>> the MyHDL code base is. I don't know that I'd have the time to dig >>>>>> deep enough into it to contribute such a patch. >>>>>> >>>>> >>>>> I am having a hard time following you. At one point >>>>> you comment >>>>> >>>>> "since this process seems easy to automate ..." >>>>> >>>>> then you comment >>>>> >>>>> "... the amount of steps would be great" >>>>> (implying difficulty) >>>>> >>>>> But if it is easy to automate why would we be concerned >>>>> with the number of steps? >>>> >>>> I should have been more clear: >>>> - The process "seems easy to automate" according to what you said. >>>> - But it _currently_ requires a great number of steps since it must be >>>> performed _manually_ (which does not necessarily mean that it would be >>>> hard, just tiresome). >>>> >>>> That is, currently MyHDL does not provide a way to make this without >>>> too much effort, but apparently (from what you said) it should be >>>> possible to make it automatic. >>>> >>>>> I also get confused if you are only interested in an >>>>> existing solution or you are willing to experiment and >>>>> be part of a development. This conversation seems to >>>>> bounce back and forth between wanting a working solution >>>>> and "testing the waters". I am never sure which I am >>>>> replying to. Given the comments above, I assume you >>>>> are mainly interested in existing and working solutions. >>>>> >>>>> Maintaining hierarchy during conversion is a reasonable >>>>> feature request. But the priority of the feature? And >>>>> the best path forward? I think it is safe to say, given >>>>> the resources available this feature will not be added >>>>> any time soon. I think you are simply trying to stimulate >>>>> conversation and ideas (which is good!). But I don't believe >>>>> anyone has the bandwidth to experiment and implement the >>>>> feature. >>>> >>>> I'm mostly interested on working solutions, but since it seems there >>>> are none (at least not experimental ones), I want to spur the >>>> conversation some and show that there are people (at least one! :-) >>>> interested on this feature. >>>> >>>> As for contributing I have a few small patches ready that I will send >>>> to the list shortly. These address some of small issues regarding VHDL >>>> code generation that I identified on another email. >>>> >>>> Cheers, >>>> >>>> Angel >>>> >>> >>> Angel, >>> >>> Make sure you review the "Guide for Developers": >>> http://www.myhdl.org/doku.php/dev:patches >>> >>> Jan D. has put together a comprehensive guide for contributing >>> to the project. >>> >>> Also note, Jan D. has the final say on all bundles submitted. >>> >>> Thanks for interest in contributing! >>> >>> Regards, >>> Chris >> >> OK, I did not know about that document. Sorry. >> >> Apparently it seems Jan prefers to receive bundles directly on his >> email address. I sent a patch series to the list because that is the >> way things are done on the tortoisehg and on the mercurial mailing >> list itself. The document seems to suggest that it is ok to send >> patches to the list for discussion though, so I guess what I did is >> kind of ok. >> >> Cheers, >> >> Angel >> > > I usually send patches/bundles directly to the mailing-list > (good or bad). The issue can be if it is large for some > reason. I don't believe it is bad to send patches to the > mailing-list. > > .chris OK, I will not need to resend them then :-) I tried to run the tests on my windows PC. The core tests run fine but I have trouble running the VHDL conversion tests (which are the most interesting ones for my patches). I was able to run the VHDL conversion tests, but I got 5 passes and 40 failures _without_ my patches. With my patches I get the same result. This is the output of running py.test on the myhdl\test\conversion\toVHDL folder: $ /c/Python27/Scripts/py.test ============================= test session starts ============================== platform win32 -- Python 2.7.2 -- pytest-2.2.4 collecting ... collected 45 items test_custom.py FFFF.. test_enum.py F test_loops.py . test_newcustom.py FFFF.. test_ops.py FFFFFFFFFFFFFF test_signed.py FFFFFFFFFFFFFFFFF =================================== FAILURES =================================== __________________________________ testIncRef __________________________________ def testIncRef(): > assert conversion.verify(customBench, incRef) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(customBench, incRef) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_custom.py:248: AssertionError ------------------------------- Captured stderr -------------------------------- customBench.vhd:59:14:warning: universal integer bound must be numeric literal or attribute customBench.vhd:63:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration custombench_ghdl Conversion verification failed ___________________________________ testInc ____________________________________ def testInc(): > assert conversion.verify(customBench, inc) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(customBench, inc) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_custom.py:251: AssertionError ------------------------------- Captured stderr -------------------------------- customBench.vhd:59:14:warning: universal integer bound must be numeric literal or attribute customBench.vhd:63:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration custombench_ghdl Conversion verification failed ___________________________________ testInc2 ___________________________________ def testInc2(): > assert conversion.verify(customBench, inc2) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(customBench, inc2) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_custom.py:254: AssertionError ------------------------------- Captured stderr -------------------------------- ** ToVHDLWarning: Signal is driven but not read: inc_inst_nextCount customBench.vhd:64:14:warning: universal integer bound must be numeric literal or attribute customBench.vhd:68:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration custombench_ghdl Conversion verification failed ___________________________________ testInc3 ___________________________________ def testInc3(): > assert conversion.verify(customBench, inc3) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(customBench, inc3) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_custom.py:257: AssertionError ------------------------------- Captured stderr -------------------------------- ** ToVHDLWarning: Signal is driven but not read: inc_inst_inc2_inst_nextCount customBench.vhd:64:14:warning: universal integer bound must be numeric literal or attribute customBench.vhd:68:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration custombench_ghdl Conversion verification failed __________________________________ test_enum ___________________________________ def test_enum(): > assert conversion.verify(bench_enum) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(bench_enum) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_enum.py:65: AssertionError ------------------------------- Captured stderr -------------------------------- error: cannot find entity or configuration bench_enum_ghdl Conversion verification failed __________________________________ testIncRef __________________________________ def testIncRef(): > assert conversion.verify(customBench, incRef) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(customBench, incRef) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_newcustom.py:248: AssertionError ------------------------------- Captured stderr -------------------------------- customBench.vhd:59:14:warning: universal integer bound must be numeric literal or attribute customBench.vhd:63:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration custombench_ghdl Conversion verification failed ___________________________________ testInc ____________________________________ def testInc(): > assert conversion.verify(customBench, inc) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(customBench, inc) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_newcustom.py:251: AssertionError ------------------------------- Captured stderr -------------------------------- customBench.vhd:59:14:warning: universal integer bound must be numeric literal or attribute customBench.vhd:63:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration custombench_ghdl Conversion verification failed ___________________________________ testInc2 ___________________________________ def testInc2(): > assert conversion.verify(customBench, inc2) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(customBench, inc2) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_newcustom.py:254: AssertionError ------------------------------- Captured stderr -------------------------------- customBench.vhd:64:14:warning: universal integer bound must be numeric literal or attribute customBench.vhd:68:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration custombench_ghdl Conversion verification failed ___________________________________ testInc3 ___________________________________ def testInc3(): > assert conversion.verify(customBench, inc3) == 0 E assert 1 == 0 E + where 1 = <myhdl.conversion._verify._VerificationClass object at 0x02451830>(customBench, inc3) E + where <myhdl.conversion._verify._VerificationClass object at 0x02451830> = conversion.verify test_newcustom.py:257: AssertionError ------------------------------- Captured stderr -------------------------------- customBench.vhd:64:14:warning: universal integer bound must be numeric literal or attribute customBench.vhd:68:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration custombench_ghdl Conversion verification failed ________________________________ testBinary[0] _________________________________ m = 4, n = 4 def checkBinary(m, n): > assert verify(binaryBench, m, n) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, 4, 4) test_ops.py:172: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:92:14:warning: universal integer bound must be numeric literal or attribute binaryBench.vhd:131:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed ________________________________ testBinary[1] _________________________________ m = 5, n = 3 def checkBinary(m, n): > assert verify(binaryBench, m, n) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, 5, 3) test_ops.py:172: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:92:14:warning: universal integer bound must be numeric literal or attribute binaryBench.vhd:115:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed ________________________________ testBinary[2] _________________________________ m = 2, n = 6 def checkBinary(m, n): > assert verify(binaryBench, m, n) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, 2, 6) test_ops.py:172: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:92:14:warning: universal integer bound must be numeric literal or attribute binaryBench.vhd:107:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed ________________________________ testBinary[3] _________________________________ m = 8, n = 7 def checkBinary(m, n): > assert verify(binaryBench, m, n) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, 8, 7) test_ops.py:172: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:92:14:warning: universal integer bound must be numeric literal or attribute binaryBench.vhd:355:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed _______________________________ testMultiOps[0] ________________________________ m = 4, n = 4, p = 4 def checkMultiOps(m, n, p): > assert verify(multiBench, m, n, p) == 0 E assert 1 == 0 E + where 1 = verify(multiBench, 4, 4, 4) test_ops.py:264: AssertionError ------------------------------- Captured stderr -------------------------------- multiBench.vhd:45:14:warning: universal integer bound must be numeric literal or attribute multiBench.vhd:99:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration multibench_ghdl Conversion verification failed _______________________________ testMultiOps[1] ________________________________ m = 5, n = 3, p = 2 def checkMultiOps(m, n, p): > assert verify(multiBench, m, n, p) == 0 E assert 1 == 0 E + where 1 = verify(multiBench, 5, 3, 2) test_ops.py:264: AssertionError ------------------------------- Captured stderr -------------------------------- multiBench.vhd:45:14:warning: universal integer bound must be numeric literal or attribute multiBench.vhd:63:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration multibench_ghdl Conversion verification failed _______________________________ testMultiOps[2] ________________________________ m = 3, n = 4, p = 6 def checkMultiOps(m, n, p): > assert verify(multiBench, m, n, p) == 0 E assert 1 == 0 E + where 1 = verify(multiBench, 3, 4, 6) test_ops.py:264: AssertionError ------------------------------- Captured stderr -------------------------------- multiBench.vhd:45:14:warning: universal integer bound must be numeric literal or attribute multiBench.vhd:75:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration multibench_ghdl Conversion verification failed _______________________________ testMultiOps[3] ________________________________ m = 3, n = 7, p = 4 def checkMultiOps(m, n, p): > assert verify(multiBench, m, n, p) == 0 E assert 1 == 0 E + where 1 = verify(multiBench, 3, 7, 4) test_ops.py:264: AssertionError ------------------------------- Captured stderr -------------------------------- multiBench.vhd:45:14:warning: universal integer bound must be numeric literal or attribute multiBench.vhd:75:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration multibench_ghdl Conversion verification failed _______________________________ testUnaryOps[0] ________________________________ m = 4 def checkUnaryOps(m): > assert verify(unaryBench, m) == 0 E assert 1 == 0 E + where 1 = verify(unaryBench, 4) test_ops.py:326: AssertionError ------------------------------- Captured stderr -------------------------------- unaryBench.vhd:37:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration unarybench_ghdl Conversion verification failed _______________________________ testUnaryOps[1] ________________________________ m = 7 def checkUnaryOps(m): > assert verify(unaryBench, m) == 0 E assert 1 == 0 E + where 1 = verify(unaryBench, 7) test_ops.py:326: AssertionError ------------------------------- Captured stderr -------------------------------- unaryBench.vhd:37:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration unarybench_ghdl Conversion verification failed ________________________________ testAugmOps[0] ________________________________ m = 4, n = 4 def checkAugmOps(m, n): > assert verify(augmBench, m, n) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, 4, 4) test_ops.py:466: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:98:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[1] ________________________________ m = 5, n = 3 def checkAugmOps(m, n): > assert verify(augmBench, m, n) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, 5, 3) test_ops.py:466: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:98:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[2] ________________________________ m = 2, n = 6 def checkAugmOps(m, n): > assert verify(augmBench, m, n) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, 2, 6) test_ops.py:466: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:98:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[3] ________________________________ m = 8, n = 7 def checkAugmOps(m, n): > assert verify(augmBench, m, n) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, 8, 7) test_ops.py:466: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:98:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed _______________________________ testBinaryOps[0] _______________________________ Ll = -254, Ml = 236, Lr = 0, Mr = 4 def checkBinaryOps( Ll, Ml, Lr, Mr): > assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, -254, 236, 0, 4) test_signed.py:188: AssertionError ------------------------------- Captured stderr -------------------------------- ** ToVHDLWarning: Signal is not driven: RightShift binaryBench.vhd:69:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed _______________________________ testBinaryOps[1] _______________________________ Ll = -128, Ml = 128, Lr = -128, Mr = 128 def checkBinaryOps( Ll, Ml, Lr, Mr): > assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, -128, 128, -128, 128) test_signed.py:188: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:69:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed _______________________________ testBinaryOps[2] _______________________________ Ll = -53, Ml = 25, Lr = -23, Mr = 123 def checkBinaryOps( Ll, Ml, Lr, Mr): > assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, -53, 25, -23, 123) test_signed.py:188: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:69:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed _______________________________ testBinaryOps[3] _______________________________ Ll = -23, Ml = 145, Lr = -66, Mr = 12 def checkBinaryOps( Ll, Ml, Lr, Mr): > assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, -23, 145, -66, 12) test_signed.py:188: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:69:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed _______________________________ testBinaryOps[4] _______________________________ Ll = 23, Ml = 34, Lr = -34, Mr = -16 def checkBinaryOps( Ll, Ml, Lr, Mr): > assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, 23, 34, -34, -16) test_signed.py:188: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:69:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed _______________________________ testBinaryOps[5] _______________________________ Ll = -54, Ml = -20, Lr = 45, Mr = 73 def checkBinaryOps( Ll, Ml, Lr, Mr): > assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, -54, -20, 45, 73) test_signed.py:188: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:69:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed _______________________________ testBinaryOps[6] _______________________________ Ll = -25, Ml = -12, Lr = -123, Mr = -66 def checkBinaryOps( Ll, Ml, Lr, Mr): > assert verify(binaryBench, Ll, Ml, Lr, Mr ) == 0 E assert 1 == 0 E + where 1 = verify(binaryBench, -25, -12, -123, -66) test_signed.py:188: AssertionError ------------------------------- Captured stderr -------------------------------- binaryBench.vhd:69:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration binarybench_ghdl Conversion verification failed _______________________________ testUnaryOps[0] ________________________________ m = 4 def checkUnaryOps(m): > assert verify(unaryBench, m) == 0 E assert 1 == 0 E + where 1 = verify(unaryBench, 4) test_signed.py:266: AssertionError ------------------------------- Captured stderr -------------------------------- unaryBench.vhd:37:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration unarybench_ghdl Conversion verification failed _______________________________ testUnaryOps[1] ________________________________ m = 7 def checkUnaryOps(m): > assert verify(unaryBench, m) == 0 E assert 1 == 0 E + where 1 = verify(unaryBench, 7) test_signed.py:266: AssertionError ------------------------------- Captured stderr -------------------------------- unaryBench.vhd:37:14:warning: universal integer bound must be numeric literal or attribute error: cannot find entity or configuration unarybench_ghdl Conversion verification failed ________________________________ testAugmOps[0] ________________________________ Ll = -254, Ml = 236, Lr = 0, Mr = 4 def checkAugmOps( Ll, Ml, Lr, Mr): > assert verify(augmBench, Ll, Ml, Lr, Mr) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, -254, 236, 0, 4) test_signed.py:412: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:60:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[1] ________________________________ Ll = -128, Ml = 128, Lr = -128, Mr = 128 def checkAugmOps( Ll, Ml, Lr, Mr): > assert verify(augmBench, Ll, Ml, Lr, Mr) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, -128, 128, -128, 128) test_signed.py:412: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:60:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[2] ________________________________ Ll = -53, Ml = 25, Lr = -23, Mr = 123 def checkAugmOps( Ll, Ml, Lr, Mr): > assert verify(augmBench, Ll, Ml, Lr, Mr) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, -53, 25, -23, 123) test_signed.py:412: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:60:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[3] ________________________________ Ll = -23, Ml = 145, Lr = -66, Mr = 12 def checkAugmOps( Ll, Ml, Lr, Mr): > assert verify(augmBench, Ll, Ml, Lr, Mr) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, -23, 145, -66, 12) test_signed.py:412: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:60:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[4] ________________________________ Ll = 23, Ml = 34, Lr = -34, Mr = -16 def checkAugmOps( Ll, Ml, Lr, Mr): > assert verify(augmBench, Ll, Ml, Lr, Mr) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, 23, 34, -34, -16) test_signed.py:412: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:60:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[5] ________________________________ Ll = -54, Ml = -20, Lr = 45, Mr = 73 def checkAugmOps( Ll, Ml, Lr, Mr): > assert verify(augmBench, Ll, Ml, Lr, Mr) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, -54, -20, 45, 73) test_signed.py:412: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:60:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed ________________________________ testAugmOps[6] ________________________________ Ll = -25, Ml = -12, Lr = -123, Mr = -66 def checkAugmOps( Ll, Ml, Lr, Mr): > assert verify(augmBench, Ll, Ml, Lr, Mr) == 0 E assert 1 == 0 E + where 1 = verify(augmBench, -25, -12, -123, -66) test_signed.py:412: AssertionError ------------------------------- Captured stderr -------------------------------- augmBench.vhd:60:14:warning: universal integer bound must be numeric literal or attribute <class 'myhdl.StopSimulation'>: No more events error: cannot find entity or configuration augmbench_ghdl Conversion verification failed _______________________________ testExpressions ________________________________ def testExpressions(): > assert verify(expressionsBench) == 0 E assert 1 == 0 E + where 1 = verify(expressionsBench) test_signed.py:503: AssertionError ------------------------------- Captured stderr -------------------------------- error: cannot find entity or configuration expressionsbench_ghdl Conversion verification failed ===================== 40 failed, 5 passed in 16.95 seconds ===================== Cheers, Angel |
