[myhdl-list] [PATCH RFC] toVHDL: add signal attribute support

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349884148 -7200
# Branch 0.8-dev
# Node ID cdd0b98bc565ce08c5ab47417551e7719313d9ce
# Parent  58ac2e97c7efbe7e3c9784b8ac25218daa056e40
toVHDL: add signal attribute support

This adds a new setAttribute() method to the Signal type, which lets the user
set attributes that will be set on the VHDL output.

In order to make it easy to avoid declaring the same attribute more than once,
all the signal attributes are written toguether, after all signal declarations.

The setAttribute() Signal method has the following interface:

    Signal.setAttribute(attribute_name, attribute_value, [attribute_type])

If attribute_type is not set it will default to string.

diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py
--- a/myhdl/_Signal.py
+++ b/myhdl/_Signal.py
@@ -107,10 +107,10 @@
                  '_code', '_tracing', '_nrbits', '_checkVal', 
                  '_setNextVal', '_copyVal2Next', '_printVcd', 
                  '_driven' ,'_read', '_name', '_used', '_inList',
-                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs'
+                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs',
+                 'setAttribute', '_attributes'
                 )
 
-
     def __init__(self, val=None):
         """ Construct a signal.
 
@@ -118,6 +118,7 @@
         
         """
         self._init = deepcopy(val)
+        self._attributes = {}
         self._val = deepcopy(val)
         self._next = deepcopy(val)
         self._min = self._max = None
@@ -300,6 +301,9 @@
     def _printVcdVec(self):
         print >> sim._tf, "b%s %s" % (bin(self._val, self._nrbits), self._code)
 
+    def setAttribute(self, name, value, attribute_type=None):
+        self._attributes[name] = (value, attribute_type)
+
     ### use call interface for shadow signals ###
     def __call__(self, left, right=None):
         s = _SliceSignal(self, left, right)
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -286,6 +286,22 @@
 
 constwires = []
 
+def _writeAttributes(f, siglist):
+    declared_attributes = set()
+    for s in siglist:
+        for name in s._attributes:
+            value, attribute_type = s._attributes[name]
+            if attribute_type is None:
+                # consider all attributes strings by default
+                attribute_type = 'string'
+                if isinstance(value, int):
+                    attribute_type = 'integer'
+            if name not in declared_attributes:
+                declared_attributes.add(name)
+                print >> f, "    attribute %s : %s;" % (name, attribute_type)
+            
+                value = '"%s"' % value
+            print >> f, "    attribute %s of %s: signal is %s" % (name, s._name, value)
 
 def _writeSigDecls(f, intf, siglist, memlist):
     del constwires[:]
@@ -329,6 +345,9 @@
         t = "t_array_%s" % m.name
         print >> f, "    type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
         print >> f, "    signal %s: %s;" % (m.name, t)
+
+    _writeAttributes(f, siglist + memlist)
+
     print >> f
 
 def _writeCompDecls(f,  compDecls):