[myhdl-list] [PATCH 2 of 3] toVHDL: indent signal declarations
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jandecaluwe
From: Angel E. <ang...@gm...> - 2012-10-10 15:48:22
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# HG changeset patch # User Angel Ezquerra <ang...@gm...> # Date 1349882392 -7200 # Branch 0.8-dev # Node ID 54652ce766a4f8ee6318e662a5394df20a899711 # Parent 3c6f870ae4b826ac462778d3d61a6477928957ef toVHDL: indent signal declarations It is common practice to indent signal declarations (e.g. VHDL indent tools often indent them). This also makes the generated VHDL code a bit cleaner. diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -303,7 +303,7 @@ ) # the following line implements initial value assignments # print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val)) - print >> f, "signal %s: %s%s;" % (s._name, p, r) + print >> f, " signal %s: %s%s;" % (s._name, p, r) elif s._read: # the original exception # raise ToVHDLError(_error.UndrivenSignal, s._name) @@ -312,7 +312,7 @@ category=ToVHDLWarning ) constwires.append(s) - print >> f, "signal %s: %s%s;" % (s._name, p, r) + print >> f, " signal %s: %s%s;" % (s._name, p, r) for m in memlist: if not m._used: continue @@ -327,8 +327,8 @@ r = _getRangeString(m.elObj) p = _getTypeString(m.elObj) t = "t_array_%s" % m.name - print >> f, "type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r) - print >> f, "signal %s: %s;" % (m.name, t) + print >> f, " type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r) + print >> f, " signal %s: %s;" % (m.name, t) print >> f def _writeCompDecls(f, compDecls): |