[myhdl-list] [PATCH 1 of 3] toVHDL: improve indentation of type definitions

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349882135 -7200
# Branch 0.8-dev
# Node ID 3c6f870ae4b826ac462778d3d61a6477928957ef
# Parent  41d4a8b1380479a3c93e2ecbf7cb90f7dc955119
toVHDL: improve indentation of type definitions

Up until now the indentation of type definitions was be wrong. VHDL type
definitions span multiple lines but only only their first line was indented.

diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -222,7 +222,7 @@
     _sortedEnumTypeList = list(_enumTypeSet)
     _sortedEnumTypeList.sort(cmp=lambda a, b: cmp(a._name, b._name))
     for t in _sortedEnumTypeList:
-        print >> f, "    %s" % t._toVHDL()
+        print >> f, "    %s" % t._toVHDL().replace('\n', '\n    ')
     print >> f
     print >> f, "end package pck_%s;" % intf.name
     print >> f