Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Angel E. <ang...@gm...>]

On Wed, Oct 10, 2012 at 2:25 PM, Christopher Felton
<chr...@gm...> wrote:
> <snip>
>>
>>
>>>> Anyway, since this process seems easy to automate (I can't really
>>>> tell, since I don't really understand it), the obvious question is why
>>>> not make MyHDL itself automate it for us? That should put to rest the
>>>> question of generating hierarchical VHDL or Verilog code which seems
>>>> to crop up regularly on this list and on other online discussions
>>>> about MyHDL!
>>>
>>> The obvious question is why someone interested in a
>>> feature doesn't propose a MEP and a patch?
>>
>> That is a fair point. I am still "testing the waters" with MyHDL so to
>> speak, so for now I am just raising the concerns that I come up with.
>>
>> I could try to write a MEP but first I'd like to see if there is some
>> consensus that this could be a worthy idea (as I believe it is). Also,
>> what would be the preferred way to indicate that a group of generators
>> should be grouped into an entity and placed on their own file?
>>
>> For example, in the case that you described, imagine that you had had
>> a magic wand that let you modify MyHDL in a way that you could have
>> avoided all the manual work involved in solving your problem. How
>> would you have liked to be able to tell MyHDL that you wanted to place
>> "submodule" on its own file?
>>
>> Contributing a patch is another matter though. I am quite busy
>> contributing to TortoiseHg at the moment and I don't know how complex
>> the MyHDL code base is. I don't know that I'd have the time to dig
>> deep enough into it to contribute such a patch.
>>
>
> I am having a hard time following you.  At one point
> you comment
>
>     "since this process seems easy to automate ..."
>
> then you comment
>
>     "... the amount of steps would be great"
>     (implying difficulty)
>
> But if it is easy to automate why would we be concerned
> with the number of steps?

I should have been more clear:
- The process "seems easy to automate" according to what you said.
- But it _currently_ requires a great number of steps since it must be
performed _manually_ (which does not necessarily mean that it would be
hard, just tiresome).

That is, currently MyHDL does not provide a way to make this without
too much effort, but apparently (from what you said) it should be
possible to make it automatic.

> I also get confused if you are only interested in an
> existing solution or you are willing to experiment and
> be part of a development.  This conversation seems to
> bounce back and forth between wanting a working solution
> and "testing the waters".  I am never sure which I am
> replying to.  Given the comments above, I assume you
> are mainly interested in existing and working solutions.
>
> Maintaining hierarchy during conversion is a reasonable
> feature request.  But the priority of the feature?  And
> the best path forward?  I think it is safe to say, given
> the resources available this feature will not be added
> any time soon.  I think you are simply trying to stimulate
> conversation and ideas (which is good!).  But I don't believe
> anyone has the bandwidth to experiment and implement the
> feature.

I'm mostly interested on working solutions, but since it seems there
are none (at least not experimental ones), I want to spur the
conversation some and show that there are people (at least one! :-)
interested on this feature.

As for contributing I have a few small patches ready that I will send
to the list shortly. These address some of small issues regarding VHDL
code generation that I identified on another email.

Cheers,

Angel