[myhdl-list] Some comments about using MyHDL to create a simple module

[Angel E. <ezq...@gm...>]

Hi,

As I said on my previous email I am trying to create a simple module
using MyHDL and I am trying to see how it feels compared to writing
the same module directly in VHDL. I'm taking notes as I go along. I
already sent some comments regarding the VHDL code that MyHDL
generates and now I have some comments about using MyHDL itself.
Hopefully some of you may find these interesting.

1. When you make a mistake, the toVHDL function raises an error which
spits out a long callback list. Out of this list only the last part is
(usually) interesting (I think!). For example:

C:\myhdl_test>python sync_module.py
Traceback (most recent call last):
  File "sync_module.py", line 56, in <module>
    sync_inst = toVHDL(sync_module, rst, clk, tcell_cnt, mode_2pps_width, sync_i
n, sync_out)
  File "C:\python26\lib\site-packages\myhdl\conversion\_toVHDL.py", line 150, in
 __call__
    genlist = _analyzeGens(arglist, h.absnames)
  File "C:\python26\lib\site-packages\myhdl\conversion\_analyze.py", line 176, i
n _analyzeGens
    v.visit(tree)
  File "C:\python26\lib\ast.py", line 231, in visit
    return visitor(node)
  File "C:\python26\lib\site-packages\myhdl\conversion\_analyze.py", line 1019,
in visit_Module
    self.generic_visit(node)
  File "C:\python26\lib\ast.py", line 239, in generic_visit
    self.visit(item)
  File "C:\python26\lib\ast.py", line 231, in visit
    return visitor(node)
  File "C:\python26\lib\site-packages\myhdl\conversion\_analyze.py", line 1112,
in visit_FunctionDef
    self.visit(n)
  File "C:\python26\lib\ast.py", line 231, in visit
    return visitor(node)
  File "C:\python26\lib\site-packages\myhdl\conversion\_analyze.py", line 710, i
n visit_If
    self.visitList(node.else_)
  File "C:\python26\lib\site-packages\myhdl\conversion\_misc.py", line 163, in v
isitList
    self.visit(n)
  File "C:\python26\lib\ast.py", line 231, in visit
    return visitor(node)
  File "C:\python26\lib\site-packages\myhdl\conversion\_analyze.py", line 506, i
n visit_Assign
    self.visit(target)
  File "C:\python26\lib\ast.py", line 231, in visit
    return visitor(node)
  File "C:\python26\lib\site-packages\myhdl\conversion\_analyze.py", line 758, i
n visit_Name
    self.setName(node)
  File "C:\python26\lib\site-packages\myhdl\conversion\_analyze.py", line 783, i
n setName
    self.raiseError(node, _error.UnboundLocal, n)
  File "C:\python26\lib\site-packages\myhdl\conversion\_misc.py", line 150, in r
aiseError
    raise ConversionError(kind, msg, info)
myhdl.ConversionError: in file sync_module.py, line 49:
    Not supported: Augmented signal assignment

I think this is unnecessary. It would be better if MyHDL only showed
you the last part. Perhaps there could be a "verbose" or "debug" mode
that could be used to show the whole thing in those (rare?) cases in
which it were necessary to debug the problem (which I guess would only
be necessary when you hit a bug on MyHDL itself). That is, it'd be
nice if this is what you got:

C:\myhdl_test>python sync_module.py
myhdl.ConversionError: in file sync_module.py, line 49:
    Not supported: Augmented signal assignment

2. I was surprised that that you cannot use the "+=" operator on
synthesizable code. Could't MyHDL convert:

~~~
s_2pps_counter.next += 2
~~~

into:

~~~
s_2pps_counter.next =  s_2pps_counter + 2
~~~
?

3. The error that you get when you forget to assign to the "next"
property of a signal is a bit weird. You get:

    Local variable may be referenced before assignment: s_2pps_counter

It is kind of obvious on hindsight but it took me a little while to
understand what the error was.

4. I don't see a way to set signal attributes that can be passed along
to the synthesizer (e.g. to specify that a memory should be
implemented as a block ram, etc). I believe someone (Jan?) told me
about this a while ago on this list but I cannot find the original
email on my inbox, sorry!

5. This may be a wacky idea, but perhaps MyHDL could show its strengh
over VHDL by making it easier to go to the "next" state on a state
machine. Currently (both on VHDL and MyHDL) you must explicitly set
next state on a state machine, even though this often means just going
to the "next" state on the state list (this is particularly true for
pipelined designs).

It would be cool (and something that VHDL cannot do) if enums had a
"next()" or "nextstate()" method that gave you the "next" state on the
state list. That is, if you had:

t_state = enum('INIT', 'WAIT', 'WORK')

Then you could do:

if state == t_state.INIT:
    # initalize stuff
    state.next = state.nextstate() # which would return t_state.WAIT
elif state == t_state.WAIT:
    # wait for something to happen, then:
    state.next = state.nextstate()
else:
    # do some work, then
    state.next = t_state.WAIT
    # You could mix the use of nextstate() with regular state jumps.
    # Here state.nextstate() would have returned INIT (or raise an error?)
    # so it would not make sense to jump to it.

This could make it simpler to introduce new intermediate states
without having to modify most of your existing code. On the other hand
it may be error prone... As I said, this is just an idea.

In VHDL and even on MyHDL you can do this today if you use a numeric
value rather than an actual enum, but then you lose the readability of
the "if/elif" clauses.


This is all I got so far.

Cheers,

Angel