Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Christopher F. <chr...@gm...>]

On 9/28/2012 9:21 AM, Tom Dillon wrote:
>
> On 09/28/2012 08:53 AM, Christopher Felton wrote:
>> On 9/28/2012 8:25 AM, Tom Dillon wrote:
>>> Angel,
>>>
>>> My quick answer is to start in one of two areas.
>>>
>>> 1. Use MyHDL to design and test modules that are included in your VHDL
>>> design. Make the modules general purpose with parameters so that they
>>> are easily reused. The test bench and module source will be in MyHDL.
>>>
>>> 2. Use MyHDL as a test bench for existing VHDL modules. You can get far
>>> better test coverage quicker with this approach. Of course now we are
>>> talking about co-simulation, so you will have to be using a VHDL
>>> simulator that is supported or modify an existing interface to work with
>>> your simulator (usually not much work). I use Aldec Riviera and it works
>>> great.
>>>
>>> I would start there.
>>>
>>> Tom
>>>
>> Tom,
>>
>> Are you using cosimulation with Aldec and VHDL?  If so did you have to
>> do small mods for the VHPI interface?
>>
>> Regards,
>> Chris
>>
> Chris,
>
> Great question. It had been so long since I did that I forgot. I am
> using VPI (not VHPI) to connect to the Riviera simulator. I have a mixed
> mode version of Riviera so that allows me to simulate Verilog or VHDL
> modules.
>
> I suspect VHPI would work as well.
>
> Tom
>
>

Strangely modelsim does not appear to support VPI with
VHDL directly, you have to use their FLI interface.

But I do not know what happens if you do a mixed Verilog/VHDL
sim in Modelsim.  My guess is, you have to do a Verilog
mixed VHDL sim (top-level Verilog) and it would work.
If that is true, the quick path for MyHDL-VHDL cosim
would be this approach (mixed verilog/vhdl requires
Modelsim SE or Questa).

Regards,
Chris