Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Christopher F. <chr...@gm...>]

On 9/28/2012 8:25 AM, Tom Dillon wrote:
> Angel,
>
> My quick answer is to start in one of two areas.
>
> 1. Use MyHDL to design and test modules that are included in your VHDL
> design. Make the modules general purpose with parameters so that they
> are easily reused. The test bench and module source will be in MyHDL.
>
> 2. Use MyHDL as a test bench for existing VHDL modules. You can get far
> better test coverage quicker with this approach. Of course now we are
> talking about co-simulation, so you will have to be using a VHDL
> simulator that is supported or modify an existing interface to work with
> your simulator (usually not much work). I use Aldec Riviera and it works
> great.
>
> I would start there.
>
> Tom
>

Tom,

Are you using cosimulation with Aldec and VHDL?  If so did you have to 
do small mods for the VHPI interface?

Regards,
Chris