Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Angel E. <ang...@gm...>]

On Fri, Sep 28, 2012 at 2:16 PM, Christopher Felton
<chr...@gm...> wrote:
> On 9/28/2012 2:26 AM, Angel Ezquerra wrote:
>> Hi,
>>
>> For the past couple of years I've been following the MyHDL project
>> with a lot of interest. I've been subscribed to the mailing list and
>> followed many of the interesting discussions in here. I've done a few
>> of the examples on my spare time and I have read the documentation a
>> couple of times.
>>
>> I really like the language. I find it very clear and simply way nicer
>> than VHDL, which is what we use in our projects where I work. I have
>> quite a lot of experience with Python, and at work I sometimes use it
>> with some of its great scientific packages, such as simpy, scipy,
>> matplotlib, etc, mainly for simulation purposes although most of my
>> colleagues use Matlab for this.
>>
>> That being said, I have trouble coming up with a good way to integrate
>> MyHDL into our existing workflows. I'm looking for advice here to see
>> if there is a way that we could use MyHDL to improve our productivity.
>>
> <snip>
>
> My quick two cents is that you adopt the "IP" developed
> with MyHDL approach.  You start using the tool this way.
> Your co-workers might never know you are using MyHDL.

I'm not sure I understand what you mean. Do you mean that I would
write my code on MyHDL, generate the VHDL and publish the generated
VHDL as an "IP"?

If that is the case I fear that the fact that the automatically
generated code is flat may be a problem. Depending on how big are the
modules that I work on it the resulting VHDL could be pretty big,
couldn't it? I guess my colleagues would find that odd :-P

> As you indicate, there are some short comings to this
> approach.  One of the items you suggested is using MyHDL
> for top-level simulation/verification (cosimulation with
> VHDL).  What VHDL simulator are you using?

We currently use Modelsim and ISim, on Windows.

> Since you have an established flow, I imagine it will be
> hard to radically change.  You will need to methodically
> work MyHDL in.  My best guess, this would mean developing
> individual pieces with MyHDL then incorporating into the
> system.

That is what I'd like to do but I don't quite see a good way to do so,
given the concerns that I stated on my first email.

> Then second, you could start building your system sim and
> verification in MyHDL.  This will require VHDL cosim.  There
> might be enough interest to spend some cycles getting VHDL
> cosim working, the hold back has been access to commerical
> simulators.

Being able to write test benches in python would be awesome, that is
for sure! I really dislike how limited is VHDL for IO and other non
synthesizable stuff.

Angel