Re: [myhdl-list] Integrating MyHDL into a more "traditional" design work flow

[Christopher F. <chr...@gm...>]

On 9/28/2012 2:26 AM, Angel Ezquerra wrote:
> Hi,
>
> For the past couple of years I've been following the MyHDL project
> with a lot of interest. I've been subscribed to the mailing list and
> followed many of the interesting discussions in here. I've done a few
> of the examples on my spare time and I have read the documentation a
> couple of times.
>
> I really like the language. I find it very clear and simply way nicer
> than VHDL, which is what we use in our projects where I work. I have
> quite a lot of experience with Python, and at work I sometimes use it
> with some of its great scientific packages, such as simpy, scipy,
> matplotlib, etc, mainly for simulation purposes although most of my
> colleagues use Matlab for this.
>
> That being said, I have trouble coming up with a good way to integrate
> MyHDL into our existing workflows. I'm looking for advice here to see
> if there is a way that we could use MyHDL to improve our productivity.
>
<snip>

My quick two cents is that you adopt the "IP" developed
with MyHDL approach.  You start using the tool this way.
Your co-workers might never know you are using MyHDL.

As you indicate, there are some short comings to this
approach.  One of the items you suggested is using MyHDL
for top-level simulation/verification (cosimulation with
VHDL).  What VHDL simulator are you using?

Since you have an established flow, I imagine it will be
hard to radically change.  You will need to methodically
work MyHDL in.  My best guess, this would mean developing
individual pieces with MyHDL then incorporating into the
system.

Then second, you could start building your system sim and
verification in MyHDL.  This will require VHDL cosim.  There
might be enough interest to spend some cycles getting VHDL
cosim working, the hold back has been access to commerical
simulators.

Regards,
Chris