Re: [myhdl-list] VHDL Cosimulation was: MyHDL: Why Do We Need Signal Assignments?

[David B. <dav...@ya...>]

The simulator is MODELSIM / QUESTA which is embedded in Actel Libero !!!  

David







--- On Tue, 9/25/12, Christopher Felton <chr...@gm...> wrote:

From: Christopher Felton <chr...@gm...>
Subject: Re: [myhdl-list] VHDL Cosimulation was: MyHDL: Why Do We Need Signal Assignments?
To: myh...@li...
Date: Tuesday, September 25, 2012, 4:09 PM

On 9/25/2012 3:02 PM, David Blubaugh wrote:
> Is there a way to call VHDL within a MyHDL script file??
>
> I want to simulate a preexisting VHDL file within MyHDL !!!
>
> David
>

Which VHDL simulator are you using?

>
>
>
>
> --- On Tue, 9/25/12, Jan Decaluwe <ja...@ja...> wrote:
>
> From: Jan Decaluwe <ja...@ja...>
> Subject: Re: [myhdl-list] MyHDL: Why Do We Need Signal Assignments?
> To: myh...@li...
> Date: Tuesday, September 25, 2012, 12:24 PM
>
> On 09/25/2012 12:49 AM, Angel Ezquerra wrote:
>>
>> On Sep 23, 2012 10:13 AM, "Jan Decaluwe" <ja...@ja...
>> <mailto:ja...@ja...>> wrote:
>>>
>>> I have justed posted a blog about signal assignments, why they are
>>> needed and who MyHDL implements them.
>>>
>>> I feel these concepts are often misunderstood, which leads to
>>> misunderstandings later on. I hope you like it.
>>>
>>> http://www.programmableplanet.com/author.asp?section_id=2438&doc_id=251153&
>>
>>>
>>
>>> -- th Co Jan Decaluwe
>>
>> Very nice and clear post. It covers some very basic stuff, yet this
>> is something that I think a lot of people do not really understand.
>
> Right, and judging from the lack of response, I'm not sure they
> do now :-) But anyway, this is done so I can refer to it in the
> future.
>
>> I remember that, when I first read about MyHDL, I found the way
>> signal assignments work (by assigning to the "next" property) very
>> intuitive. I'm sure a lot of people will find your article very
>> enlightening. I sure did, and I forwarded it to the members of my
>> team.
>
> Excellent!
>
>
>
>
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