Re: [myhdl-list] Filename path support for toVHDL and toVerilog functions

[Christopher F. <chr...@gm...>]

On 9/20/12 2:16 AM, Shankar Giri Venkita Giri wrote:
> Maybe we should be adding path support for toVHDL and toVerilog conversion functions in myhdl. This will allow us to generate HDL at user defined path and not pollute current directory. Since these functions have a variable arglist in the end, the path argument has to come in the beginning, which means API breaks. Thoughts?
>
> -Shankar
>

I like the idea and it might not be too difficult to implement.  If you 
use the current toV*.name attribute (see example below) the conversion 
functions would need to do some limited path/name checking.  Else, a new 
toV*.path (or output) attribute could be added.

In [125]: mkdir conversion_output

In [126]: def ex(clock, reset, x, y):
      ...:     @always_seq(clock.posedge, reset=reset)
      ...:     def hdl():
      ...:         x.next = y + y
      ...:     return hdl

In [127]: clock = Signal(bool(0))
      ...: reset = ResetSignal(bool(0), active=0, async=True)
      ...: x = Signal(intbv(0, min=-7, max=8))
      ...: y = Signal(intbv(0, min=2*x.min, max=2*x.max))
      ...: toVerilog.name = os.path.join('conversion_output/', 'new_name.v')
      ...: toVerilog(ex, clock, reset, x, y)
      ...:
---------------------------------------------------------------------------
IOError                                   Traceback (most recent call ...
IOError: [Errno 2] No such file or directory: 
'tb_conversion_output/new_name.v.v'


Regards,
Chris