Re: [myhdl-list] Proposal: Cycle accurate software decorator

[Christopher F. <chr...@gm...>]

On 9/10/2012 3:51 PM, Norbo wrote:
> hey i just had an idea about a new decorator something like:
> @cycle_software
> it came across me when i was implementing a statemachine. To implement the
> statemachine i really was
> thinking in software. Like, while some condition is not met, stay in this
> state, and if this and this happens go
> to another state. I realised that a "if" and "while" statement would be
> enougth to describe the statemachine.
> And i realised that it would have been way easier to write down the state
> machine with "if and while" available and no
> need to write down all the additional states and trying to give them
> meaningfull names.
>
<snip>
> this state it would then go to the THIRD state
> 				
>
> So what i think is, that it should be quit possible to convert a
> description like this ( only with "if" and "while" at first) to a valid
> statemachine, which then would be convertible to vhdl or verilog.
> This would rise a couple of questions
>

I am not sure I know what you mean by "thinking in software" vs. the 
implied "thinking in hardware"?  Do you simply mean procedural vs. 
concurrent representations?  In this context the "software thinking" is 
intended to suggest higher abstraction and procedural?

Regards,
Chris