[myhdl-list] Proposal: Cycle accurate software decorator

[Norbo <Nor...@gm...>]

hey i just had an idea about a new decorator something like:  
@cycle_software
it came across me when i was implementing a statemachine. To implement the  
statemachine i really was
thinking in software. Like, while some condition is not met, stay in this  
state, and if this and this happens go
to another state. I realised that a "if" and "while" statement would be  
enougth to describe the statemachine.
And i realised that it would have been way easier to write down the state  
machine with "if and while" available and no
need to write down all the additional states and trying to give them  
meaningfull names.


I start with an example

@cycle_software(clk.posedge)
def func_software():
    while 1:
	while not Recieved:     ## would be FIRST state which is left if Received  
is True
	    pass
	
	Data_header.next=Rx_data  ## would be SECOND state which is left  
imidiatly after it is entered
	Count.next=0              ## could be SECOND state but then der should be  
some mechanisem to group expressions
			          ## or every instruction gets its own state with one clock  
cycle inbetween them.

	while not (Count==100):   ## would be in THIRD state,state would go to  
FIRST state if Count==100
             while not Recieved:   ## would be in THIRD state, would go to  
FOURTH state if Received==True
	       pass

	    if Data_header[0]:     ## would all be in the FOURTH state
	    	Ram1[Count].next=Rx_data
             else:
                 Ram2[Count].next=Rx_data
             Count.next=Count+1     ## or an extra state for this, from  
this state it would then go to the THIRD state
				

So what i think is, that it should be quit possible to convert a  
description like this ( only with "if" and "while" at first) to a valid  
statemachine, which then would be convertible to vhdl or verilog.
This would rise a couple of questions

But the way bigger question would be how to integrate this code into  
simulation?
Some thoughts i had for this:
  * use byteplay or something like this and insert a yield clk.posedge  
between every line or at the positions needed
  * do the yield clk.posedge in the  ".next" or use something other than  
the ".next" like ".nextSoftware"
  but then the "while not Recieved: pass" loop would still need to yield  
something.
could be replaced with "while not Recieved: PASS()" and define it with

def PASS():
      yield clk.posedge

but the converter would then need to ignore this.
hmm....

anyway i think it could somehow be possible and get at some (very very  
distant day) a very cool feature.

greetings
Norbo