Re: [myhdl-list] func.verilog_code

[Christopher F. <chr...@gm...>]

On 8/28/12 4:17 AM, Jan Decaluwe wrote:
> On 08/28/2012 05:29 AM, Christopher Felton wrote:
>> I am wondering if I ran into an issue using the
>> .verilog_code and .verilog_instance function attributes?
>> When I use either of these attributes all the ports
>> are treated as inputs.  I have observed this with 0.8dev
>> (some print modifications) as well as 0.7.
>
> Some issues:
>
> To infer signal direction from user-defined code properly, the
> convertor needs some help:
>
> http://www.myhdl.org/doc/current/manual/conversion.html#user-defined-code
>
> This is required because the convertor skips any code
> marked as user-defined.
>
> Second, the .verilog_instance is not documented - I
> vaguely remember that there were some issues that I
> had to revisit but I haven't done that yet. If you
> think it's useful and if can be turned into a robust
> feature we can revisit it.
>
>
<snip>

I realized it was undocumented but you had sent a detailed post to the 
newgroup indicating how you had used the .vhdl_instance or 
.verilog_instance to stitch together a bunch of MyHDL modules.  I 
thought I would give it a go.

Yes, I think it is a very useful feature.  In my case it is redundant to 
rewrite the actual verilog/vhdl code since it is only instantiating an 
FPGA IP.  I found it less error prone to use the .*_instance vs. *_code 
when simply instantiating (black box) other modules.

Regards,
Chris