Re: [myhdl-list] func.verilog_code

[Christopher F. <chr...@gm...>]

On 8/28/12 1:00 AM, Wesley New wrote:
> Are you forgetting:
>
> <output>.driven = "wire"
>
> Regards
>
> Wes

Perfect, thanks I knew it was something basic I was forgetting.

Regards,
Chris