[myhdl-list] always_seq

[Christopher F. <chr...@gm...>]

I apologize in advance to the lack of information
but I was modifying some old code and decide to give
the always_seq a whirl in the code.  I ran into a small
issue.  If I have a description like the following,
the generated Verilog does not have the correct /begin/ /end/.

MyHDL description:

    from myhdl import *

     def p_edge(clock, reset, slow_sig, sig_posedge):
         _delay = Signal(False)
         @always_seq(clock.posedge, reset=reset)
         def hdl_edge():
             _delay.next = slow_sig
             if not _delay and slow_sig:
                 sig_posedge.next = True
             else:
                 sig_posedge.next = False

         return hdl_edge

     def convert():
         clock = Signal(False)
         reset = ResetSignal(True, active=0, async=True)
         sig = Signal(False)
         edge = Signal(False)
         toVerilog(p_edge, clock, reset, sig, edge)

     if __name__ == '__main__':
         convert()


Generated Verilog:

     always @(posedge clock, negedge reset) begin: P_EDGE_HDL_EDGE
         if (reset == 0) begin
             sig_posedge <= 0;
             _delay <= 0;
         end
         else
             _delay <= slow_sig;
             if (((!_delay) && slow_sig)) begin
                 sig_posedge <= 1'b1;
             end
             else begin
                 sig_posedge <= 1'b0;
             end
         end

     endmodule


Regards,
Chris