Re: [myhdl-list] toVerilog and kwargs

[Jan D. <ja...@ja...>]

On 08/11/2012 12:40 AM, Per Karlsson wrote:
> On Fri, Aug 10, 2012 at 11:06 PM, Jan Decaluwe <ja...@ja...
> <mailto:ja...@ja...>> wrote:
>
> On 08/10/2012 02:37 PM, Per Karlsson wrote:
>> Let's say I want to make a design that can realize chips with
>> between 0 and 64 PCI-Express interfaces. How can I write that
>> parametrized top module in MyHDL?
>
> That is not a problem at all.
>
> Once again, the only problem is conversion.
>
>
> Without conversion there won't be any ASICs! :)
>
> Let me ask a question in return: how would you deal with the
> parametrization in VHDL/Verilog?
>
>
> I would do it using a parametrized perl or python pre-processor
> capable of generating each of the needed configurations as static
> verilog.

Ok. Presumably, you would provide some way for the user
to specify a particular configuration, in particular:

1) the port names you want in VHDL/Verilog
2) the port order
3) the port types

In MyHDL, 1) and 2) are specified by the the top-level
function. 3) by the Signals you call it with.

The reason to do it like that is that it is conceptually
identical to what you always do when instantiating in
MyHDL: calling a function. However, it is true that this
particular function call is more restrictive than others,
because of the additional functionality listed above.

In a workflow, one could develop a fully parametrized
module, and only provide a top-level wrapper as late as
possible,as a way to configure a specific instance for
conversion.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com