Re: [myhdl-list] toVerilog and kwargs

[Jan D. <ja...@ja...>]

On 08/10/2012 02:37 PM, Per Karlsson wrote:
> Hm, without kwargs in toVerilog I still don't see how I can make a
> parametrized design for conversion in pure MyHDL without a
> preprocessor that generates the MyHDL code for the toplevel (which in
> all fairness would be fine I guess).
>
> Let's say I want to make a design that can realize chips with between
> 0 and 64 PCI-Express interfaces. How can I write that parametrized
> top module in MyHDL? /Per
>
> ps. I haven't looked at the source code yet so I shouldn't venture
> into that discussion, but what is keeping us from looking into the
> kwarg dictionary for the port names?

One issue would be that a dictionary doesn't specify an
order, which is likely something that you want to control
when going to Verilog/VHDL.


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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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