Re: [myhdl-list] toVerilog and kwargs

[Per K. <bas...@gm...>]

On Fri, Aug 10, 2012 at 11:06 PM, Jan Decaluwe <ja...@ja...> wrote:

> On 08/10/2012 02:37 PM, Per Karlsson wrote:
> > Let's say I want to make a design that can realize chips with between
> > 0 and 64 PCI-Express interfaces. How can I write that parametrized
> > top module in MyHDL?
>
> That is not a problem at all.
>
> Once again, the only problem is conversion.


Without conversion there won't be any ASICs! :)


> Let me ask a question in return: how would you deal with the
> parametrization in VHDL/Verilog?


I would do it using a parametrized perl or python pre-processor capable of
generating each of the needed configurations as static verilog.

However, I am sick of mixing languages---it's a mess!
MyHDL holds the promise of replacing System-C for system simulation, perl
for pre-processing, verilog/VHDL for leaf-design, and Modelsim/VCS for
module test, and thus give me the integrated design environment I crave!
Perhaps MyHDL 0.7 can do it, perhaps it cannot. This is what I'm trying to
figure out.
/Per

ps. Besides conversion the main thing I'm worried about is simulation speed
for system simulation. But I'm too in fascinated with being able to write
the system model and the synthesizable model in the same language and use
them interchangeably that I'm prepared to overlook that for now. I
guess I'll have to write a toSystemC function eventually... :)