Re: [myhdl-list] toVerilog and kwargs

[Norbo <Nor...@gm...>]

Am 10.08.2012, 14:37 Uhr, schrieb Per Karlsson <bas...@gm...>:

> Hm,
> without kwargs in toVerilog I still don't see how I can make a  
> parametrized
> design for conversion in pure MyHDL without a preprocessor that generates
> the MyHDL code for the toplevel (which in all fairness would be fine I
> guess).

i did something like this to give a adjustable number of arguments to the  
toVHDL function, bilding up the string of the code
with the number of arguments i wannted and then exec it.


	for i in range(NumberArguments):
	    code="A"+str(i)+"= Signal(bool(0))"
	    exec(code)

	code="toVHDL(PicoBoard"
	for i in range(NumberArguments):
     		code=code+",A"+str(i)
	code=code+")"
	exec(code)


...hm probably not the best solution.


greetings norbo