[myhdl-list] about MEP 107

[Jose I. V. <jo...@dt...>]

Hi all,
I'd like to know about the current status of MEP 107 or if there is someone
working on it, since I could understand from some messages in the list that
at least part of the work might be in progress.

In the following paragraphs I'd like to show the source of my interest on
this MEP:
I'm currently developing a set of libraries upon MyHDL to perform System on
Chip integration by using components hosted in public repositories in an
easy way. My aim is to develop a tool able to make it easier the use and
reuse of components under free licenses such as those found in Opencores in
a very straightforward way. The idea is that the components will be hosted
at on-line repositories, in a similar way to debian packages, wrapped with
an XML description similar to IP-Xact, but simpler and more
parameterizable. This way, the SoC description is performed in an object
oriented/structural paradigm. Instances are objects created by simple calls
to convenience functions like i.e. cpu=get_instance("openrisc"), and
interconnection between components is performed through helper methods like
comp1.get_wb().connect("wb_int", comp2.get_wb()). The the network of
components and links can be converted or cosimulated.
One of the key aspects of this structural paradigm is that you can model
components as objects in a very parameterizable way, like in example a
logic gate which a undefined number of inputs as the simplest case. Or
components with an undefined number of Wishbone interfaces in a more
complex case. I've already developed an XML description format similar to
IP-Xact capable to describe components with this level of
parameterizability and I have classed in Python to work with this
descriptions and use components hosted in the remote repositories.
Currently I'm working in the integration of all of this into MyHDL.
My first take, assuming that this external components in the first stage
will only be cosimulated or converted since there is no MyHDL models
available was to create an abstract class called ExternalComponent. This
class models and behaves as any possible external component using the
information found in the XML description, to understand the structure of
the component's interface, ports, set of files, parameters, etc. So
depending on the content of the XML file, the objects will expose a
particular interface. This point is where MEP107 plays a key role for me.
The component's port list is unknown until a particular component is
instances, so it is passed as **kwargs. So being able to dynamically add
attributes to the each object instance, that can be used inside the
generators could allow to also add a MyHDL simulatable model, since by now,
neither object attributes nor kwargs accesses, can be used inside
generators. Another solution would be binding kwargs accesses to variables
outside generators, but is not possible in this case because the members of
kwargs are unknown until a particular component is instanced.
By now I've come over it using several hacks, in the first step I made some
modifications to MyHDL core to be able to use kwargs inside generators, but
I discarded it because it was not a  general solution and I wanted to use a
MyHDL without modifications. In the second try I used a trick, assigning to
locals()["varname"]=kwargs["varname"] I could dynamically bind kwargs to
variables that could be used inside generators, but this trick is
deprecated in Python 3.0. Finally, I found in MEP 107 to be a much more
general solution capable to go over my problem and open a wide range of new
modeling techniques.

Jose.

José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64