Re: [myhdl-list] toVerilog and kwargs

[Per K. <bas...@gm...>]

Hm,
without kwargs in toVerilog I still don't see how I can make a parametrized
design for conversion in pure MyHDL without a preprocessor that generates
the MyHDL code for the toplevel (which in all fairness would be fine I
guess).

Let's say I want to make a design that can realize chips with between 0 and
64 PCI-Express interfaces. How can I write that parametrized top module in
MyHDL?
/Per

ps. I haven't looked at the source code yet so I shouldn't venture into
that discussion, but what is keeping us from looking into the kwarg
dictionary for the port names?

On Fri, Aug 10, 2012 at 1:12 PM, Jan Decaluwe <ja...@ja...> wrote:

> On 08/09/2012 06:42 PM, Per Karlsson wrote:
> > Ah, I see! (And thanks for the explanation!)
> >
> > Well, if I cannot use classes as interfaces, and I cannot
> > automatically explode lists of ports at the top for conversion, then
> > I'll feel severely hampered.
>
> The top level function is special and restrictive in conversion,
> that is all.
>
> It uses the arg names as the spec of the port names in Verilog
> and VHDL. Where else should it get them, e.g. in case of varargs?
> But I concede there should be an error message that varargs and
> kwargs are not supported in the top level function.
>
> For the rest, you can basically do what you want. Use classes
> a interfaces, pass modules as a parameter to other modules,
> whatever. Just don't try to convert such functions as the
> top-level.
>
> The only restrictions apply to the syntax *inside* generator
> code, see the manual. The basic trick is therefore to do all
> the complex stuff and lookup outside generator code ("at
> elaboration time").
>
> For example, you cannot use attribute lookup inside a generator
> but you can do it outside. This may be a good idea in general:
> it makes the "action" code smaller, and it only does the lookup
> once at elaboration time, instead of all the time during
> simulation.
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
>
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