Re: [myhdl-list] toVerilog and kwargs

[Jan D. <ja...@ja...>]

On 08/09/2012 06:42 PM, Per Karlsson wrote:
> Ah, I see! (And thanks for the explanation!)
>
> Well, if I cannot use classes as interfaces, and I cannot
> automatically explode lists of ports at the top for conversion, then
> I'll feel severely hampered.

The top level function is special and restrictive in conversion,
that is all.

It uses the arg names as the spec of the port names in Verilog
and VHDL. Where else should it get them, e.g. in case of varargs?
But I concede there should be an error message that varargs and
kwargs are not supported in the top level function.

For the rest, you can basically do what you want. Use classes
a interfaces, pass modules as a parameter to other modules,
whatever. Just don't try to convert such functions as the
top-level.

The only restrictions apply to the syntax *inside* generator
code, see the manual. The basic trick is therefore to do all
the complex stuff and lookup outside generator code ("at
elaboration time").

For example, you cannot use attribute lookup inside a generator
but you can do it outside. This may be a good idea in general:
it makes the "action" code smaller, and it only does the lookup
once at elaboration time, instead of all the time during
simulation.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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