Re: [myhdl-list] toVerilog and kwargs

[Jose I. V. <jo...@dt...>]

Hi!
it's happening because of the method used by myhdl to extract the port list
at the top level function.
In the first case, the function passed to toVerilog has a fully defined arg
list, in the second case it only has args and kwargs.
If you debug your example, you will see that
_AnalyzeTopFuncVisitor->visit_FunctionDef() in the first case
node.args.args contains the arguments in the prototype of wrap(), but in
the second case it is empty since only args and kwargs were declared in the
prototype of kwarg_wrap()

I think that this strange effect is limited to the top level function. If
you redefine the first case in the following way you will see kwarg_wrap()
working as expected. The problem is not in kwarg_wrap(), but in the fact
that the functions passed as top level to toVerilog() need an explicit
declaration of the arguments that will be in the port list.

def wrap(d,q,clk,rstn):
    kwargs={
        'd': d,
        'q': q,
        'clk': clk,
        'rstn': rstn
        }
    wrap_inst = kwarg_wrap(**kwargs)
    return wrap_inst

Another discussion would be if this limitation is stopping some nice
features like the possibility to describe highly parameterizable designs in
myhdl and what could be done to go over it. I'd like to know what other
people think about this. Maybe that changes like the proposed by Chris
Felton in MEP107 (Conversion of Attribute Signal Containers) could be
useful for this purpose.

Jose.

José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64



On Wed, Aug 8, 2012 at 10:54 PM, Per Karlsson <bas...@gm...>wrote:

> Hi!
> I'm about to embark on a fairly substantial ASIC/FPGA IP design project.
> The design is meant to be highly customizable and I'm in the process of
> figuring out if we should go for a home brewn preprocessor or for MyHDL.
> So here is my first in what will---in all likelihood---be a string of
> silly questions:
>
> Below I have made a flop with asynchronous reset, and then wrapped it in
> two different empty shells.
> The first using normal named arguments, and the second using **kwargs.
> For simulation both work, but for conversion to verilog only the first is
> OK.
> The kwargs wrapper looses the ports in conversion.
>
> Do any of you guys have an idea why?
> /Per
>
> from myhdl import *
>
> def flop(d,q,clk,rstn):
>     @always(clk.posedge, rstn.negedge)
>     def flop_rtl():
>         if not rstn:
>             q.next = 0
>         else:
>             q.next = d
>     return flop_rtl
>
> def wrap(d,q,clk,rstn):
>     kwargs={
>         'd': d,
>         'q': q,
>         'clk': clk,
>         'rstn': rstn
>         }
>     wrap_inst = flop(**kwargs)
>     return wrap_inst
>
> def kwarg_wrap(*args, **kwargs):
>     wrap_inst = flop(*args, **kwargs)
>     return wrap_inst
>
>
> def generate_flop():
>      clk  = Signal(bool(0))
>     rstn = Signal(bool(0))
>     d    = Signal(bool(0))
>     q    = Signal(bool(0))
>
>     toVerilog(wrap, d=d, q=q, clk=clk, rstn=rstn)
>
>     top_args = ()
>     top_kwargs={
>         'd': d,
>         'q': q,
>         'clk': clk,
>         'rstn': rstn
>         }
>
>      toVerilog(kwarg_wrap, *top_args, **top_kwargs)
>
> generate_flop()
>
>
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