[myhdl-list] toVerilog and kwargs

[Per K. <bas...@gm...>]

Hi!
I'm about to embark on a fairly substantial ASIC/FPGA IP design project.
The design is meant to be highly customizable and I'm in the process of
figuring out if we should go for a home brewn preprocessor or for MyHDL.
So here is my first in what will---in all likelihood---be a string of silly
questions:

Below I have made a flop with asynchronous reset, and then wrapped it in
two different empty shells.
The first using normal named arguments, and the second using **kwargs.
For simulation both work, but for conversion to verilog only the first is
OK.
The kwargs wrapper looses the ports in conversion.

Do any of you guys have an idea why?
/Per

from myhdl import *

def flop(d,q,clk,rstn):
    @always(clk.posedge, rstn.negedge)
    def flop_rtl():
        if not rstn:
            q.next = 0
        else:
            q.next = d
    return flop_rtl

def wrap(d,q,clk,rstn):
    kwargs={
        'd': d,
        'q': q,
        'clk': clk,
        'rstn': rstn
        }
    wrap_inst = flop(**kwargs)
    return wrap_inst

def kwarg_wrap(*args, **kwargs):
    wrap_inst = flop(*args, **kwargs)
    return wrap_inst


def generate_flop():
    clk  = Signal(bool(0))
    rstn = Signal(bool(0))
    d    = Signal(bool(0))
    q    = Signal(bool(0))

    toVerilog(wrap, d=d, q=q, clk=clk, rstn=rstn)

    top_args = ()
    top_kwargs={
        'd': d,
        'q': q,
        'clk': clk,
        'rstn': rstn
        }

    toVerilog(kwarg_wrap, *top_args, **top_kwargs)

generate_flop()