Re: [myhdl-list] Testbench Template

[Christopher F. <chr...@gm...>]

On 8/3/12 8:39 AM, Christopher Felton wrote:
> On 8/3/12 8:14 AM, Geoffrey Brown wrote:
>> Thanks,  that's a help.  But I notice you don't trace when doing
>> co-simulation so I guess you haven't seen
>> in practice the error that started this thread.   It is the case that
>> tracing is forbidden when conversion is
>> performed in the same program execution (why ???), but tracing does
>> work with co-simulation except for the
>> annoying error at the end.
>>
>> Geoffrey
>
> I missed the fact the the error was caused when
> tracing with cosimulation.  With cosimulation you
> have two simulation engines running, MyHDL sim
> and the Icarus (or whatever Verilog sim) running.
>
> If you want/need to trace the verilog signals you
> need to enable tracing in the verilog sim eng.  You
> can do this by adding $dumpvars to the tb_*.v file.
>
> You can simultaneously trace the signals in your
> MyHDL testbench, you just need a separate function.
>
>      g_tb = traceSignals(tb_test)
>      g_dut = Cosimulation(...)
>      # need to manually create/modify the tb_test
>
>
> Note, I was planning on posting the /testbench/
> template example.  It was intended to be an example
> but not necessarily to solve this exact issue.
>
> Regards,
> Chris
>

I modified the example to trace the testbecn
and enable tracing in the cosimulation verilog.
This will generate two different vcd files.  I
didn't get any errors/warnings.

To run the example:
     >> python test_myadder.py --cosim --trace


Note, the attached files are only useful for
cosimulation.  It will only trace the testbench
in the MyHDL sim.  If you trace in only MyHDL
sim you will not get any of the DUT signals.

Hope this helps,
Chris