Re: [myhdl-list] Testbench Template

[Christopher F. <chr...@gm...>]

On 8/3/12 8:14 AM, Geoffrey Brown wrote:
> Thanks,  that's a help.  But I notice you don't trace when doing
> co-simulation so I guess you haven't seen
> in practice the error that started this thread.   It is the case that
> tracing is forbidden when conversion is
> performed in the same program execution (why ???), but tracing does
> work with co-simulation except for the
> annoying error at the end.
>
> Geoffrey

I missed the fact the the error was caused when
tracing with cosimulation.  With cosimulation you
have two simulation engines running, MyHDL sim
and the Icarus (or whatever Verilog sim) running.

If you want/need to trace the verilog signals you
need to enable tracing in the verilog sim eng.  You
can do this by adding $dumpvars to the tb_*.v file.

You can simultaneously trace the signals in your
MyHDL testbench, you just need a separate function.

    g_tb = traceSignals(tb_test)
    g_dut = Cosimulation(...)
    # need to manually create/modify the tb_test


Note, I was planning on posting the /testbench/
template example.  It was intended to be an example
but not necessarily to solve this exact issue.

Regards,
Chris

>
> On Fri, Aug 3, 2012 at 8:58 AM, Christopher Felton
> <chr...@gm...> wrote:
>> On 7/31/12 10:50 PM, Christopher Felton wrote:
>>>
>>> I have been using a simple testbench template
>>> for small single module tests.  I use this testbench
>>> template so that I can quickly add basic test stimulus
>>> to a module.  From the testbench I can do operations
>>> that require similar setup.
>>>
>>>     >> python test_.py trace
>>>     >> python test_.py convert
>>>     >> python test_.py cosim
>>>
>>> Note, I usually have a more complicated test environment
>>> (only as complicated as needed and no more) for full
>>> designs.  In addition to the *full* verification
>>> environment I typically have individual module tests
>>> that use the template.
>>>
>>> I attached the template and an example using a simple
>>> adder.  Might be useful (might not).  Feel free to
>>> comment, always room for improvement.  This is a
>>> template that needs to be manually modified and uses
>>> some features only available in 0.8dev branch.
>>>
>>> Regards,
>>> Chris
>>>
>>>
>>
>> I modified the /testbench/ template to be a class
>> which is more reusable.  Also, used the Python
>> argparser for the command line options.
>>
>>
>> Using the same example as the previous post the
>> CLI is:
>>
>>     python test_myadder.py -h
>>     usage: test_myadder.py [-h] [--trace] [--cosim] [--convert]
>>                            [-Tclk CLOCK_PERIOD]
>>
>>     Testbench
>>
>>     optional arguments:
>>       -h, --help            show this help message and exit
>>       --trace               enable testbench tracing (create VCD file)
>>       --cosim               run cosimulation
>>       --convert             convert the module
>>       -Tclk CLOCK_PERIOD, --clock_period CLOCK_PERIOD
>>                             set the clock period
>>
>> Again, this is intended to streamline the creation
>> of tests for small single module designs.
>>
>> Regards,
>> Chris