Re: [myhdl-list] Testbench Template

[Geoffrey B. <geo...@gm...>]

Thanks,  that's a help.  But I notice you don't trace when doing
co-simulation so I guess you haven't seen
in practice the error that started this thread.   It is the case that
tracing is forbidden when conversion is
performed in the same program execution (why ???), but tracing does
work with co-simulation except for the
annoying error at the end.

Geoffrey

On Fri, Aug 3, 2012 at 8:58 AM, Christopher Felton
<chr...@gm...> wrote:
> On 7/31/12 10:50 PM, Christopher Felton wrote:
>>
>> I have been using a simple testbench template
>> for small single module tests.  I use this testbench
>> template so that I can quickly add basic test stimulus
>> to a module.  From the testbench I can do operations
>> that require similar setup.
>>
>>    >> python test_.py trace
>>    >> python test_.py convert
>>    >> python test_.py cosim
>>
>> Note, I usually have a more complicated test environment
>> (only as complicated as needed and no more) for full
>> designs.  In addition to the *full* verification
>> environment I typically have individual module tests
>> that use the template.
>>
>> I attached the template and an example using a simple
>> adder.  Might be useful (might not).  Feel free to
>> comment, always room for improvement.  This is a
>> template that needs to be manually modified and uses
>> some features only available in 0.8dev branch.
>>
>> Regards,
>> Chris
>>
>>
>
> I modified the /testbench/ template to be a class
> which is more reusable.  Also, used the Python
> argparser for the command line options.
>
>
> Using the same example as the previous post the
> CLI is:
>
>    python test_myadder.py -h
>    usage: test_myadder.py [-h] [--trace] [--cosim] [--convert]
>                           [-Tclk CLOCK_PERIOD]
>
>    Testbench
>
>    optional arguments:
>      -h, --help            show this help message and exit
>      --trace               enable testbench tracing (create VCD file)
>      --cosim               run cosimulation
>      --convert             convert the module
>      -Tclk CLOCK_PERIOD, --clock_period CLOCK_PERIOD
>                            set the clock period
>
> Again, this is intended to streamline the creation
> of tests for small single module designs.
>
> Regards,
> Chris
>
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